VHDL-FPGA-Verilog List Page 4001

VHDL-FPGA-Verilog list

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VHDL Downloaded：0: EMP 7128-based digital phase-measuring instrument measuring instrument phase
Date : 2025-05-26 Size : 9kb User : YAGIC
48_fir Downloaded：0: The design of the digital base-band shaping filter with reference to IS-95 standard design, the input signal to 4 times over mining. IS-95 standards as follows: one pass-band frequency is 590Khz, passband wave the size o
Date : 2025-05-26 Size : 89kb User : 刘强
55593412100vhd Downloaded：0: VHDL programming examples, a total of 95 examples. 1_adder 2_adder 3_mul 4_comp 5_mux2 6_reg 7_shiftreg
Date : 2025-05-26 Size : 778kb User : migao
Sparten3Epaomadeng Downloaded：0: Xilinx Sparten3E Starter Kit through the verification process, development environment using ISE9.1
Date : 2025-05-26 Size : 1.21mb User : 孙斌
clk Downloaded：0: DE2 displayed in the time-consuming procedures, including the date when the minutes and seconds, you can set the start time code NiosII IDE environment to prepare
Date : 2025-05-26 Size : 1kb User : idaisy
VHDLANDSIGNALa Downloaded：0: It is a very good book for programble VHDL and digit signal book
Date : 2025-05-26 Size : 1.05mb User : sugarxyc
at96 Downloaded：0: isa bus interface can be achieved with the isa bus IO interfaces and MEMERY
Date : 2025-05-26 Size : 2kb User : jz
pci9030 Downloaded：0: pci9030 interface can be achieved with pci9030 chip interface,
Date : 2025-05-26 Size : 1kb User : jz
led Downloaded：0: 10脦禄8 露脦LED渭脛脡篓脙猫脧脭脢戮鲁脤脨貌拢卢驴脡脪脭脢渭脧脰10脦禄脢媒渭脛脧脭脢戮隆拢
Date : 2025-05-26 Size : 1kb User : jz
dct Downloaded：0: 2-D DCT-source, you can realize 8 x 8 data 2-D DCT transform
Date : 2025-05-26 Size : 5kb User : jz
d Downloaded：0: VHDL of the D flip-flop, a concise
Date : 2025-05-26 Size : 122kb User :
serial Downloaded：0: Serial port data transmission experiment, vhdl source code, complete the signal occurred, SERDES, detection circuit
Date : 2025-05-26 Size : 1kb User : yew

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