VHDL-FPGA-Verilog List Page 4002

VHDL-FPGA-Verilog list

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uart_0 Downloaded：0: Asynchronous serial communication UART Interface Design, Verilog HDL procedures essential embedded Oh
Date : 2025-05-26 Size : 5kb User : 白雪
sdram_0 Downloaded：0: SDRAM procedures of the Verilog HDL for DE2 development board, and TRDB-LCM display, oh well
Date : 2025-05-26 Size : 4kb User : 白雪
DE2_SD_Card_Audio Downloaded：0: SD card reader audio data from the VGA display. Verilog HDL language, the application of the experimental box DE2
Date : 2025-05-26 Size : 3kb User : 白雪
Dip_PB_Led Downloaded：0: Use VHDL to write防抖动function with four counters
Date : 2025-05-26 Size : 1kb User : phpkehan
05805 Downloaded：0: Wireless communication fpga design matlab, verilog code
Date : 2025-05-26 Size : 201kb User : zhangxi
fir6dlms Downloaded：1: LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
Date : 2025-05-26 Size : 1kb User : 李允
exampl Downloaded：0: A good design, everyone would like to be useful, a lot to support my
Date : 2025-05-26 Size : 111kb User : 张犇
clk-div Downloaded：0: The VHDL code for a clock divider by 27 circuit with a resulting waveform with 50% duty cycle..
Date : 2025-05-26 Size : 3kb User : 李军
txunit1 Downloaded：0: UART sends TX control circuit design, and EnableTX of the potter rate generator sends the DATAO to send it to the send buffer Tbuff, and makes the register content contain data rather than empty flag tmpTBufE= 0. When sy
Date : 2025-05-26 Size : 1kb User : 袁迎迎
an487_design_example Downloaded：0: Verlog hdl use the source code developed by SPI
Date : 2025-05-26 Size : 589kb User : zhiqiang
an485_design_example Downloaded：0: Serial peripheral interface host (verilog SPI) in an485_ch-max II CPLD
Date : 2025-05-26 Size : 305kb User : zhiqiang
miniuart.tar Downloaded：0: miniuart serial VHDL language source program
Date : 2025-05-26 Size : 6kb User : yongqin2005

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