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VHDL-FPGA-Verilog list
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Altera de2 development board to provide the matching software program, used PC, application software to control the development board peripheral device, function more comprehensive
Date : 2025-06-07 Size : 8.79mb User : 陈建

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Contains a large number of examples for learning Verilog language.
Date : 2025-06-07 Size : 347kb User : dong

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Code 2 BCD adder with the summand summand are 2 hexadecimal. Output and 10 hexadecimal. The results showed that in the LED on.
Date : 2025-06-07 Size : 8kb User : 刘锐

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VHDL realize UART communications, including sending and then call the procedure, ease of use
Date : 2025-06-07 Size : 8kb User : fdf

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fir filter design, this filter Fs for 44kHz, Fc for 10.4kHz.
Date : 2025-06-07 Size : 964kb User : fdf

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VHDL prepared ADI PLL control procedures, you can debug ADI PLL related series more than a dozen models. Pin naming and PLL control pin for the corresponding correlation.
Date : 2025-06-07 Size : 1kb User : M

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VHDL procedures VHDLram controller lib_06.zip
Date : 2025-06-07 Size : 5kb User : 刘林

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VHDL example of the procedure as many as twenty out several of the beginner there are very helpful
Date : 2025-06-07 Size : 46kb User : 刘林

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1, the normal timing functions: that is, with 24 hours timer function 2, the normal display 3, the normal transfer function 4 hours, alarm clock timer 5, the whole point timekeeping function
Date : 2025-06-07 Size : 494kb User : 杨雄

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The Verilog HDL program design tutorial source code
Date : 2025-06-07 Size : 156kb User : JI LIU

FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN Verilog and several will be a very good combination of power on
Date : 2025-06-07 Size : 6.49mb User : 赵博

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To implement the six-bit data width and to transform, compile and simulate the perfect implementation, the programming environment Quartus.
Date : 2025-06-07 Size : 1kb User : kehaiying
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