VHDL-FPGA-Verilog List Page 3948

VHDL-FPGA-Verilog list

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1. Downloaded：0: Using VHDL hardware description language completed stopwatch design, sub-module 6
Date : 2025-06-07 Size : 48kb User : 刘小
clock Downloaded：0: Two buttons control the school at the time of VHDL source clock, alarm clock and calendar with timing function
Date : 2025-06-07 Size : 2kb User : liu
BCDclock Downloaded：0: Price coverlet bcd tungsten cavity时corchorifolius tub callous钟turbulent age钟，，，时forlorn Hao Yu Rui Kun Dang 日 Xikui
Date : 2025-06-07 Size : 2kb User : liu
lift Downloaded：0: Using VHDL language elevator controller source code, to realize the police, waiting, and the optimal use of the standard line of lift movement.
Date : 2025-06-07 Size : 2kb User : wriuwru
baseonFPGA Downloaded：0: Real-time telephone billing system is the enterprise information management institutions as an important component. Introduction of a FPGA device using telephone billing system methods, and gives the design diagram and d
Date : 2025-06-07 Size : 519kb User : daifuxin
dt-VHDL Downloaded：0: Function of elevator controller This elevator controller is divided into main controller and sub-controller. The main controller is the controller inside the elevator, and each floor has a sub-controller. Functions of ma
Date : 2025-06-07 Size : 160kb User : que
uart Downloaded：0: M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx
Date : 2025-06-07 Size : 18kb User : lc
Lab1_FPGA Downloaded：0: lab1- FPGA decency in this document on how to how to use the verilog Hdl and how to make it realize in FPGA development board
Date : 2025-06-07 Size : 143kb User : 陈轩辕
Ultraedit_verilog Downloaded：0: This document provides a verilog hdl in ultra edit32 programming required in grammar
Date : 2025-06-07 Size : 30kb User : 陈轩辕
VeriRiscCPU Downloaded：0: The simple use of verilog HDL in this file enables the microcpu design and development process
Date : 2025-06-07 Size : 17kb User : 陈轩辕
diantikongzhimonichengxu Downloaded：0: An elevator control simulation program has done a good job is the image of the animation display
Date : 2025-06-07 Size : 313kb User : lc
LCAS Downloaded：0: Link Tongliang realize adjustment mechanism program, which is in MSTP in the link capacity is dynamically adjusted to achieve the key technology. Is based on the SDH in the VCAT, the transmission network in the next lett
Date : 2025-06-07 Size : 13kb User : 牧羊人

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