VHDL-FPGA-Verilog List Page 3955

VHDL-FPGA-Verilog list

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adc_verilog Downloaded：0: adc verilog Verilog prepared using sigma-delta adc examples used in the measurement adc Product category
Date : 2025-06-06 Size : 3kb User : 张鸿
verlog2 Downloaded：0: VHDL language information. Textbooks explain. For a variety of encoding rules are referred to Chao
Date : 2025-06-06 Size : 1.3mb User : 文敏
ofdm Downloaded：0: Orthogonal frequency division multiplexing realize the hardware description language, atera environment
Date : 2025-06-06 Size : 2.01mb User : 王强强
tanchishe Downloaded：0: Using VHDL language programming EPM7128SLC8-15 in a few experiments to develop on-board electric realize Snake game, with a few electric EPM7128SLC8-15 development board of the experimental samples
Date : 2025-06-06 Size : 1.03mb User : works he
serial-configuration-device(epcs1-epcs4) Downloaded：0: In the FPGA development process will encounter the problem of choice of the preparation of chips, where introduction of serial configuration devices, low cost, high-performance
Date : 2025-06-06 Size : 196kb User : sun huaiming
quartusii_handbook Downloaded：0: quartusii the development of manuals to facilitate learning quartusii
Date : 2025-06-06 Size : 21.09mb User : sun huaiming
ep2c5-pininformation Downloaded：0: ALTERA chip CycloneII the EP2C5 detailed description of the pin, developers easy to use
Date : 2025-06-06 Size : 84kb User : sun huaiming
ByteBlasterII Downloaded：0: Introduction ByteBlastrII (FPGA download circuit interface) circuit design, in accordance with circuit design, has been tried, can be used. Finally got the. Altera download original line does sell more than 1K
Date : 2025-06-06 Size : 120kb User : sun huaiming
verilog Downloaded：0: This is the Verilog hardware description language learning essential classic.
Date : 2025-06-06 Size : 458kb User : 田园
ref-sqroot Downloaded：0: The square root of IP will be open sqroot_license.txt in FEATURE 6AF8_0048 alterad 0000.00 permanent uncounted 4A689178551B VENDOR_STRING = gl15kdhm5gUPkJD7iM82mn $ $ HOSTID = ANY can be used to join!
Date : 2025-06-06 Size : 39kb User : lin
rece_7E Downloaded：0: HDLC control began to receive data to the zero mark 7E and modules for use in FPGA and E1 phase, Verilog HDL language
Date : 2025-06-06 Size : 2kb User : 刘彻
vhdlsample Downloaded：0: VHDL example of many, many examples of VHDL,
Date : 2025-06-06 Size : 165kb User : aaa

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