VHDL-FPGA-Verilog List Page 3922

VHDL-FPGA-Verilog list

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jiaozhi_and_jiejiaozhi Downloaded：0: Intertwined intertwined reconciliation module, interwoven matrix approach, and has two sets of parallel memory, you can realize continuous data stream operations, will not have data retention and loss
Date : 2025-06-08 Size : 2kb User : xiaoyuer
fft_statemachine Downloaded：0: FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower
Date : 2025-06-08 Size : 7kb User : xiaoyuer
flash_read_and_write Downloaded：0: Applicable to meet the I2C protocol flash read/write operations, only need to set to read/write number of bytes can be used directly!
Date : 2025-06-08 Size : 3kb User : xiaoyuer
mc8051 Downloaded：1: FPGA can be run on 8051 IP core, is to learn from FPGA and SPOC good information.
Date : 2025-06-08 Size : 385kb User : ygl
ads2 Downloaded：0: ADS8325caiyang konfgzhi
Date : 2025-06-08 Size : 1kb User : 远方
logvhdl Downloaded：0: altera calculated on the logarithm of the IP core.
Date : 2025-06-08 Size : 114kb User : max
3_4×4 Downloaded：0: Verilog keyboard input program for led lights display
Date : 2025-06-08 Size : 613kb User : tang
gps_jiance Downloaded：0: Combined unit GPS clock synchronization detection unit merger GPS synchronized clock detection
Date : 2025-06-08 Size : 1kb User : 远方
altera Downloaded：0: Dc to use a very good book a very good use of books dc
Date : 2025-06-08 Size : 14.57mb User : 王祁远
dds Downloaded：0: Dds realize functions, using Quartus software, sub-modules including the adder, phase-locked loop, date-rom image to the module using integrated, using ps2 keyboard to control the frequency and phase.
Date : 2025-06-08 Size : 2.72mb User : lijingfeng
highspeed Downloaded：0: Digital Clock description of the VHDL language, with high precision and good control performance
Date : 2025-06-08 Size : 1.73mb User : 张亲魄
uart_regs Downloaded：0: Can be directly downloaded to the chip used in the complete UART with FIFO procedures, vhdl language.
Date : 2025-06-08 Size : 379kb User : liujingxing

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