VHDL-FPGA-Verilog List Page 3918

VHDL-FPGA-Verilog list

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pll Downloaded：0: Using FPGA digital phase-locked loop, development environment for ISE
Date : 2025-06-09 Size : 174kb User : 冯勇
Clock Downloaded：0: Using Verilog realize an electronic clock, a template for beginners to learn Verilog.
Date : 2025-06-09 Size : 11kb User : Jason
mimasuo Downloaded：0: Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
Date : 2025-06-09 Size : 95kb User : wan
VHDL Downloaded：0: Realize four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency, magnitude controllable output (square wave A, is also a controllable duty cycle), can store arbitrary waveform feature data an
Date : 2025-06-09 Size : 9kb User : zhanyi
vhdlyuyan Downloaded：0: VHDL language description of the main description of statements and the use of methods, containing examples for learning improve
Date : 2025-06-09 Size : 81kb User : zhanyi
vhd100examples Downloaded：0: The use of VHDL language 100 examples of commonly used procedures
Date : 2025-06-09 Size : 405kb User : zhanyi
FPGAbi_ioreseach Downloaded：0: : For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, o
Date : 2025-06-09 Size : 113kb User : zhanyi
EDA Downloaded：0: Using VHDL language, and music performance procedures, examples of songs as
Date : 2025-06-09 Size : 684kb User : xiezheqi
4x4KEY Downloaded：0: First, download the board into the motherboard above .1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the functional test procedures for 4 × 4 keyboard keys specif
Date : 2025-06-09 Size : 68kb User : Jak
Reference_Design Downloaded：0: University plans altera package, including basic configuration, can be directly transplanted
Date : 2025-06-09 Size : 1.64mb User : ysh
VGA Downloaded：0: The pilot should be used in conjunction with the backplane EDA4.0. First core plate inserted EDA4.0 floor above, and then connect to VGA monitors .1. Source file stored in the src directory, QII the project file stored i
Date : 2025-06-09 Size : 57kb User : Jak
test11 Downloaded：0: In altera de1 installed on the board fat12fat16fat32 file system has been tested successfully, the direct use
Date : 2025-06-09 Size : 7.99mb User : 245680

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