VHDL-FPGA-Verilog List Page 3731

VHDL-FPGA-Verilog list

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rectangle Downloaded：0: Rectangle on the screen at the formation of the VHDL process can also be felt.
Date : 2025-06-21 Size : 184kb User : 肖
screen Downloaded：0: Read the screen coordinates of the bright spots on VHDL code, a common study.
Date : 2025-06-21 Size : 252kb User : 肖
bus Downloaded：0: Show that the expansion bus _VHDL code, a common study.
Date : 2025-06-21 Size : 188kb User : 肖
LVDS_Serdes_list_FPGA1 Downloaded：0: LVDS transmission between the FPGA using serdes interface, transfer rate up to 400m
Date : 2025-06-21 Size : 13.67mb User : linpingping
sum_ten Downloaded：0: Accumulator 10, EDA, FPGA, DDS signal generator of the phase accumulator can be used.
Date : 2025-06-21 Size : 3kb User : seasonroad
LVDS_DDR_List_FPGA2 Downloaded：1: FPGA chips ADI' s AD9779 and communication between, a total of four channels, 68 pairs of LVDS, the sampling clock is 122.88MHz
Date : 2025-06-21 Size : 790kb User : linpingping
VHDLToVerilog Downloaded：0: VHDL example of a small example of a pilot, I hope there is help on the new war
Date : 2025-06-21 Size : 169kb User : 小冰
I2C_SLAVE Downloaded：0: I2C_SLAVER FPGA
Date : 2025-06-21 Size : 8kb User : greyzhuang
check Downloaded：1: Verilog implementation using the sequence detector
Date : 2025-06-21 Size : 3kb User : huhahuha
shift_register Downloaded：0: Using Verilog implementation of the shift register, you can achieve the left, shifted to right and other functions
Date : 2025-06-21 Size : 3kb User : huhahuha
lbuff_mem Downloaded：0: delay code
Date : 2025-06-21 Size : 2kb User : hungmin
autoseller Downloaded：1: Beverage vending machine. Writing vhdl variable with automatic procedures for the sale of goods.
Date : 2025-06-21 Size : 129kb User : 朱宏亮

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