VHDL-FPGA-Verilog List Page 3733

VHDL-FPGA-Verilog list

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SingleclocksynchronousdesignmetricCNTR Downloaded：0: VHDL design using a single clock synchronization decimal CNTR Design
Date : 2025-06-21 Size : 1kb User : pengy
EP1C6_12_1_2_MOTO Downloaded：0: ALTERA series based on the cyclone motor control routine of the experiment
Date : 2025-06-21 Size : 98kb User : xulinmeng
Quartus_Clock Downloaded：0: Using Quartus hierarchical modular design digital clock
Date : 2025-06-21 Size : 9kb User : hievery1
xapp851 Downloaded：0: The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \rtl - HDL design files \sim - simulation files \synth- Synthesis related files \par - Place/Route related
Date : 2025-06-21 Size : 71kb User : 小刘
count_plus_last Downloaded：0: On the motor encoder inputs of the quadrature encoder signals 4 octave treatment, generates a new pulse count and at the same time to determine the direction of motor rotation, the output level in one direction signs sig
Date : 2025-06-21 Size : 1kb User : dengzhaoyun
ide_control Downloaded：0: Verilog three-step procedure of the IDE, but only parts of DMA, PIO required to add their own code
Date : 2025-06-21 Size : 2kb User : wang
PCI_VHDL Downloaded：0: pci vhdl
Date : 2025-06-21 Size : 27kb User : 包云兵
flash Downloaded：0: flashing led example code
Date : 2025-06-21 Size : 87kb User : nattu
freqm Downloaded：0: frequency multiplier
Date : 2025-06-21 Size : 82kb User : nattu
jc2_vhd Downloaded：0: jhonson counter using shifter
Date : 2025-06-21 Size : 54kb User : nattu
hex2rom_0241_Win32 Downloaded：0: This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).
Date : 2025-06-21 Size : 94kb User : zhangdongqing
USB2.0IP Downloaded：0: Complete Verilog language developed by USB2.0 IP core source code, including documentation
Date : 2025-06-21 Size : 202kb User : 陈润

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