VHDL-FPGA-Verilog List Page 3674

VHDL-FPGA-Verilog list

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guard_against_theft Downloaded：0: Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15 seconds if there is no pressing Key1, will be set automatically dial
Date : 2025-06-23 Size : 897kb User : 李德明
bin2bcd Downloaded：0: Binary to BCD converter
Date : 2025-06-23 Size : 1kb User : Natacho
testMem Downloaded：0: Example of a FPGA memory controler
Date : 2025-06-23 Size : 7kb User : Natacho
EDA Downloaded：0: VHDL language used to display the clock source code
Date : 2025-06-23 Size : 2kb User : shulin
Example-b3-1 Downloaded：0: ALTER FPGA/GPLD design (primary chapter) of the source, is only one part of it for public consultation, if there are other uses, please contact me
Date : 2025-06-23 Size : 852kb User : 宋振丰
lpm_mult0 Downloaded：0: Quartus2 programming environment in the VHDL language under 32* 32 high-speed computing
Date : 2025-06-23 Size : 1kb User : CAR
ADCINT Downloaded：0: Based on the VHDL language, A/D sampling control procedures, procedures for the use of state machine to achieve the
Date : 2025-06-23 Size : 163kb User : zhangzhen
NIOSII-uartprogram Downloaded：0: SOPC technology use NIOS II serial Details
Date : 2025-06-23 Size : 169kb User : wql
VHDL_fenpin Downloaded：0: Frequency for the use of FPGA design phase, including the decimal, the frequency scores of sub-
Date : 2025-06-23 Size : 315kb User : 张兆伟
NCO_based_rom Downloaded：0: Integrity of the ROM-based lookup table of the NCO have 10-bit wide of the orthogonal signal
Date : 2025-06-23 Size : 84kb User : gsg
jianbo Downloaded：0: The use of CORDIC algorithm for completion of the vector signal value and the phase mode of operation information
Date : 2025-06-23 Size : 2.03mb User : gsg
Applicatio_of_VHDL-based_FPGA_design_of_FIR_filter Downloaded：0: Applicatio_of_VHDL-based_FPGA_design_of_FIR_filters
Date : 2025-06-23 Size : 2.14mb User : gsg

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