VHDL-FPGA-Verilog List Page 3670

VHDL-FPGA-Verilog list

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pwm Downloaded：0: Pulse width modulation
Date : 2025-06-23 Size : 1kb User : mangesh.kathale
UART Downloaded：0: Universal async Transmitter Receiver
Date : 2025-06-23 Size : 1kb User : mangesh.kathale
VHDL_Hardware_Language Downloaded：0: vhdl hardware description language is fundamental to the FPGA, CPLD development of more useful people.
Date : 2025-06-23 Size : 7.56mb User : qiuxiaoxiang
cd4000x Downloaded：0: CD4000-cd4066
Date : 2025-06-23 Size : 2.31mb User : 徐科峰
DE2_demonstrations Downloaded：0: DE2 development board information, mainly his example, contain a variety of interface program, such as VGA, USB, LCD, etc.
Date : 2025-06-23 Size : 42.04mb User : 翁文天
wodeshji Downloaded：0: In the FPGA, the realization of a multi-functional digital Answer, and set up four Answer button, and a number of console button, there are points, Answer, replacement, and other functions in time
Date : 2025-06-23 Size : 440kb User : 梁贵轩
10010 Downloaded：0: verilog to achieve detection of sequence 10010
Date : 2025-06-23 Size : 1kb User : lzndcb
CRC Downloaded：0: CRC code. . . . . . . . . . . . . . . . .
Date : 2025-06-23 Size : 1kb User : lzndcb
s Downloaded：0: Beverage vending machine. . . . . . . . . . . . . . . . . . .
Date : 2025-06-23 Size : 1kb User : lzndcb
20074621282517 Downloaded：0: Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and fin
Date : 2025-06-23 Size : 4kb User : 老毕
quanjiaqi Downloaded：0: Way flow of 4 full adder 8. . . . . .
Date : 2025-06-23 Size : 1kb User : lzndcb
ds18b20 Downloaded：1: Introduction ds18b20 and timing, as well as read and write ds18b20 temperature vhdl procedure quartus compiled simulation environment
Date : 2025-06-23 Size : 14kb User : dreamy

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