VHDL-FPGA-Verilog List Page 3615

VHDL-FPGA-Verilog list

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UART_DMA Downloaded：0: NIOSII based on ALTERA s DMA transfer of the serial communication design
Date : 2025-06-26 Size : 10.82mb User : 王超
sun1602 Downloaded：0: Vhdl LCD1602 for ACTEL
Date : 2025-06-26 Size : 741kb User : sun
AVR_UARTFPGA Downloaded：0: Based on VHDL (verilog) Language Design and Implementation of UART. UART fully mimic the function of AVR, and AVR debugging interface directly to achieve. Overall integrity of the information.
Date : 2025-06-26 Size : 1.96mb User : wanglei
adder44 Downloaded：0: adder 4+ 4 bits, for use with a Altera, and 2 displays 7 segments
Date : 2025-06-26 Size : 1kb User : rich
holidaywork Downloaded：0: Machine state machine. Control work. Written by vhdl. Oh well
Date : 2025-06-26 Size : 310kb User : yamaxun
DM642_syn Downloaded：0: VHDL language used for a synchronization process, the image processing staff helpful Oh
Date : 2025-06-26 Size : 204kb User : yamaxun
Wireless_capture Downloaded：0: Many instruments are output synchronous clock, which is a district procedure burr. For very clever!
Date : 2025-06-26 Size : 25.82mb User : yamaxun
maoci Downloaded：0: Using VHDL for a procedure, used to control the frequency of the clock signal
Date : 2025-06-26 Size : 131kb User : yamaxun
sever_communicaton Downloaded：0: Serial communication program for beginner who SCM useful. Take a look at a
Date : 2025-06-26 Size : 7kb User : yamaxun
clock Downloaded：0: Clock based on the VHDL design language, the revised time alarm can be set up
Date : 2025-06-26 Size : 225kb User : 小毛
elevator Downloaded：0: VHDL prepared with a elevator control procedures, took a long time, should be very good
Date : 2025-06-26 Size : 715kb User : 小毛
adder Downloaded：0: verilog adder
Date : 2025-06-26 Size : 1015kb User : 兰书明

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