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VHDL-FPGA-Verilog list
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bch edcode and decoder
Date : 2025-06-26 Size : 171kb User : 唐娇

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SD Card Controller IP. Compatible with SD Card Agreement 2.0. With the wishbone bus interface to facilitate the use of other IP connections.
Date : 2025-06-26 Size : 24kb User : xiafei

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Examples of electronic system design languages VHDL core experimental apparatus gw48eda Hangzhou Culture Development System
Date : 2025-06-26 Size : 3.59mb User : familymxk

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no
Date : 2025-06-26 Size : 833kb User : xxl

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FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.
Date : 2025-06-26 Size : 60kb User : deadtomb

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FPGA-based VGA color display, with a total development of the reference VGA friends. Did not use DA, only 8 colors (directly connected to the VGA output of the RGB). One line, part of the market simultaneously with the c
Date : 2025-06-26 Size : 36kb User : deadtomb

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FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
Date : 2025-06-26 Size : 1.14mb User : deadtomb

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VHDL source code for test machine.
Date : 2025-06-26 Size : 846kb User : Lothrien

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A VHDL program to simulate the behaviour of a device,
Date : 2025-06-26 Size : 984kb User : Lothrien

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VHDL realization of the basic functions of electronic bell with engineering documents QUARTUE
Date : 2025-06-26 Size : 433kb User : fengyongsheng

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basics of language vhdl , how it operates etc can be laernt
Date : 2025-06-26 Size : 28kb User : DK

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Keying increase/decrease counter to 20MHz system clock by the divider available after 5M, 1M, 100K, 10K, 5K, 1K, 10Hz, 1Hz
Date : 2025-06-26 Size : 478kb User : zuoshu_2008
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