VHDL-FPGA-Verilog List Page 3618

VHDL-FPGA-Verilog list

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FSK_PSK_tiaozhidianlusheji Downloaded：0: FSK/PSK modulation circuit design, based on the vhdl and quartus2
Date : 2025-06-26 Size : 27kb User : neversee
DMA_8237A Downloaded：0: Classic DMA controller 8237A of the VHDL design, the design of the DMA controller has a high reference value.
Date : 2025-06-26 Size : 12kb User : neversee
NIOS_TFT Downloaded：0: Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
Date : 2025-06-26 Size : 13.73mb User : 涂龙
radio Downloaded：0: This procedure demo: TEA5767 non-Lipkin at the core, high-frequency processing, as well as the stereo demodulator, high-frequency phase-locked loop of the radio program as a whole, 1 support to manually enter the frequen
Date : 2025-06-26 Size : 654kb User : 涂龙
PLD(3.8M) Downloaded：0: VHDL Introduction to learning information about the details of a large number of PPT files for beginners
Date : 2025-06-26 Size : 4.66mb User : 简单
ARMloadFPGA(3) Downloaded：0: ARM LOAD FPGA, TO LET THE ARM AND FPGA TO WORK
Date : 2025-06-26 Size : 1.19mb User : sxy
frequency Downloaded：0: The program is based on FPGA hardware description language to realize the function of clock frequency, resulting in arbitrary output clock frequency.
Date : 2025-06-26 Size : 166kb User : 微微一笑
veriloghdl135 Downloaded：0: veriloghdl Tutorial 135 cases containing examples of various programming veriloghdl, very classic, hoping to help a friend in need
Date : 2025-06-26 Size : 166kb User : mieweng
ddc_FPGA Downloaded：0: Briefly introduced the design of digital down conversion, through the use of ise the xilinx software, ipcore call the realization of
Date : 2025-06-26 Size : 2.46mb User : 望天
counter1 Downloaded：0: With reset and clock enable verilo description of the decimal counter
Date : 2025-06-26 Size : 160kb User : pan
1553_enc_dec Downloaded：0: 1553B codec procedures described in verilog
Date : 2025-06-26 Size : 31kb User : pan
UART Downloaded：0: Simple UART procedure described in verilog
Date : 2025-06-26 Size : 18kb User : pan

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