VHDL-FPGA-Verilog List Page 3584

VHDL-FPGA-Verilog list

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SevenSegmentDisplay Downloaded：0: 7-end digital works two ways to achieve
Date : 2025-06-27 Size : 1kb User : 赵珑
annie5 Downloaded：0: led scrolling display of Chinese characters can be set according to different display of Chinese characters
Date : 2025-06-27 Size : 1kb User : anniepotter
paomadeng Downloaded：0: keyboard
Date : 2025-06-27 Size : 369kb User : fanglu
opencores_can Downloaded：0: CANIPCore
Date : 2025-06-27 Size : 62kb User : 陈前
bible Downloaded：0: EDA-based decoder of the 38, four elections to choose a priority, and the staircase switch circuit, including wave run.
Date : 2025-06-27 Size : 379kb User : 千语千舒
79419087q2_7_license Downloaded：1: Quartus 7.0 license
Date : 2025-06-27 Size : 6kb User : swisky
sfsdfdsf Downloaded：0: VHDL-based EDA source code of a stopwatch, counting time up to 24 hours.
Date : 2025-06-27 Size : 153kb User : 千语千舒
cpld_config Downloaded：0: spartan3e starter kit,cpld configuration file
Date : 2025-06-27 Size : 1kb User : xm
QUARTUSIIIntroduce Downloaded：0: This manual is aimed at readers of the Quartus II software for beginners, it provides an overview of programmable logic in the Quartus II design software
Date : 2025-06-27 Size : 2.95mb User : 光辉
adc_dac_normalizador_v_2 Downloaded：0: This is an examples for converting decimal number to binary
Date : 2025-06-27 Size : 2.18mb User : erix
FIR_Direkt_ak Downloaded：0: VHDL code of the direct-type 22-order FIR filter. Fa = 48 kHz, Fc = 10kHz can be under the ModelSim simulation, FPGA realization.
Date : 2025-06-27 Size : 1kb User : 李乔
FIR_Direkt_BAB_P Downloaded：0: Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
Date : 2025-06-27 Size : 1kb User : 李乔

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