VHDL-FPGA-Verilog List Page 3583

VHDL-FPGA-Verilog list

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Spartan-3_NeuralNetwork_3-layer_feedforward_backp Downloaded：0: The aim of this project is the design and implementation of a system simulating a NN in the Spartan-3 Starter Board of Xilinx. The NN will be a 3-layer feedforward backpropagation.
Date : 2025-06-27 Size : 1.41mb User : duzos
AD9826 Downloaded：0: ad9826
Date : 2025-06-27 Size : 129kb User : lin
xilinx_ref_guide Downloaded：0: Xilinx Blockset Reference Guide
Date : 2025-06-27 Size : 997kb User : hidon
fenpinqi Downloaded：0: Dual frequency many times: even several times frequency should be more familiar with all the sub-frequency, through the counter count is entirely achievable. Such as N times the frequency of even-numbered points, then by
Date : 2025-06-27 Size : 1kb User : 范尼
Verilog Downloaded：0: This is a comparison of VERILOG HDL source code commonly used devices, including registers, shifter, etc.
Date : 2025-06-27 Size : 111kb User : 张军政
rafal2 Downloaded：0: VHDL project for FPGA SPartan 3 using IseWebpack 10.1. This is an implemetation of FSM for testing 7 segment with dot point 4 digit LED display.
Date : 2025-06-27 Size : 919kb User : nukom
fft_verilog Downloaded：0: FFT IP core
Date : 2025-06-27 Size : 7kb User : chris
15-IP-core Downloaded：0: 15 IP cores
Date : 2025-06-27 Size : 4.37mb User : chris
nios Downloaded：0: altera ep2c8V2 examples timer uart I2C key interrupt etc.
Date : 2025-06-27 Size : 11.22mb User : chris
SOPC_module Downloaded：0: sopc module LCD_Delay LCD_EN delay_reset_block filter_200us
Date : 2025-06-27 Size : 20kb User : chris
verilog_m Downloaded：0: verilog m sequence
Date : 2025-06-27 Size : 6kb User : priscilla
santhosh_verilog_adder Downloaded：0: This has code off multibit Adder. IT is written in verilog. The associated test bench for the verilog code is also attatched within the rar file. Uncompress the rar file and the file name describes the function of each c
Date : 2025-06-27 Size : 9kb User : santhosh

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