VHDL-FPGA-Verilog List Page 3535

VHDL-FPGA-Verilog list

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music Downloaded：0: Through a crystal input signal, the frequency and pitch programming to achieve the output of music. After the buzzer with external line pronunciation.
Date : 2025-06-29 Size : 1kb User : yuexiangrui
PROJ Downloaded：0: 1, this experiment simulated sine function generator 2, using the logic analyzer to view waveform 3,/proj/simulation directory of simulation in modelsim
Date : 2025-06-29 Size : 1.1mb User : 杨丽杰
led_key Downloaded：0: quartus button under the control of engineering documents led
Date : 2025-06-29 Size : 180kb User : 肖
crcvhdl Downloaded：0: vhdl is to the CRC, the realization of the debugging process has
Date : 2025-06-29 Size : 286kb User : 吴能峰
vmachine Downloaded：0: Verilog code for vending machine.. Description: Vending machine ll take two quarters and distribute one of the two flavors of juice(apple or orange). Inputs: • Q : A quarter has been inserted. • O : orange juic
Date : 2025-06-29 Size : 8kb User : deepa
digital_lock Downloaded：0: Verilog code for digital combinational lock //BCAC – Unlock sequence //wrong sequence –alaram goes on and goes off only after pressin another 4 wrong buttons. //once the lock is open ,we can close the lock by pressin any
Date : 2025-06-29 Size : 7kb User : deepa
Traffic_llight_controller Downloaded：0: Consider the following variation on the traffic light controller problem. A North-South road intersects an East-West road. In addition to the Red/Yellow/Green traffic lights, the N-S road has green left-turn arrows. The
Date : 2025-06-29 Size : 6kb User : deepa
request_arbiter Downloaded：0: // Inputs------ // // DMACSREQ_i-- The 16-bit signal which stores the single request of all the 16 devices // DMACBREQ_i-- The 16-bit signal which stores the burst request of all the 16 devices // hclk_i-- Clock signal /
Date : 2025-06-29 Size : 11kb User : deepa
clock Downloaded：0: Done before the EDA curriculum design, CLOCK, may set the time, digital tube display 6
Date : 2025-06-29 Size : 1.02mb User : 王志杰
AD_ctrl Downloaded：0: VHDL Programming with FPGA-based control adc0809 and ad1674 modules, data acquisition so friends can see.
Date : 2025-06-29 Size : 2kb User : jia
ad9777_ini Downloaded：0: Verilog code to initialize the preparation of the AD9777
Date : 2025-06-29 Size : 1kb User : hanpei
vidiocpt Downloaded：0: The code for Fujitsu MV86S02 the CMOS image sensor-driven VHDL code
Date : 2025-06-29 Size : 136kb User : 王志杰

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