VHDL-FPGA-Verilog List Page 3518

VHDL-FPGA-Verilog list

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lpm_ram Downloaded：0: Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
Date : 2025-06-30 Size : 216kb User : a64577122
scramble Downloaded：0: Communication scrambling circuit VHDL Code
Date : 2025-06-30 Size : 1kb User : 江山
CNT Downloaded：0: Sub-band description of the VHDL language, giant simple and practical, one can see, from 2-16 pm band has, ah good things.
Date : 2025-06-30 Size : 1kb User : 江山
RS485EN Downloaded：0: Two-way RS485 communications, the headache is to this end they' ll pay attention to the students, this two-way communication you can solve many problems in the course of oh
Date : 2025-06-30 Size : 148kb User : 江山
Half Downloaded：0: Half-integer frequency, the frequency may be distinguished x.5, we requested to look into other frequencies.
Date : 2025-06-30 Size : 1kb User : 江山
viterbi Downloaded：0: verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Date : 2025-06-30 Size : 3kb User : xiongherui
shift_reg_ps Downloaded：0: this VHDL program can get a 64bit paralel data and make a serial data with SCLK and WCLK.
Date : 2025-06-30 Size : 1kb User : Taher Aghazadeh
shift_reg_sp Downloaded：0: this VHDL Progran get a SCLK(seril CLock) and a WCLK(Word CLOCK) with a serial data line and return a 64nits Parallel data.
Date : 2025-06-30 Size : 1kb User : Taher Aghazadeh
WRCTRL Downloaded：0: this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block
Date : 2025-06-30 Size : 2kb User : Taher Aghazadeh
SAMP_RATE Downloaded：0: this VHDL program can count and measure a time of high-level of a signal by a high-frequency refrence signal.
Date : 2025-06-30 Size : 1kb User : Taher Aghazadeh
TestLED2C5 Downloaded：0: CPU8051V1.vqm document specific examples of the use of CPU8051V1.vqm documents, quartusii software for single-chip embedded in the exercises and the use of
Date : 2025-06-30 Size : 301kb User : zhouqing
voltage Downloaded：0: FPGA control through the digital voltage meter design, the realization of VHDL, the preparation of the source code
Date : 2025-06-30 Size : 120kb User : sunruili

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