VHDL-FPGA-Verilog List Page 3515

VHDL-FPGA-Verilog list

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FPGA Downloaded：0: the ppt for designing FPGA
Date : 2025-06-30 Size : 115kb User : 史小犇
HPI Downloaded：0: HPI based on CPLD/FPGA instrument
Date : 2025-06-30 Size : 2.16mb User : ld
DHT22 Downloaded：0: The Quartus II software is written in the Verilog HDL language and communication of temperature and humidity sensors DHT2x code. There are detailed notes. DHT2x mainly for one-way bus communication is converted to 8-bit
Date : 2025-06-30 Size : 1.22mb User : yuantielei
cpld Downloaded：0: CPLD-based control logic of the bus, completely correct by the debug
Date : 2025-06-30 Size : 44kb User : ld
state_machine_watchdog Downloaded：0: State machine based on the CPLD/FPGA valuable watchdog proce
Date : 2025-06-30 Size : 635kb User : ld
etester_zcx1002 Downloaded：0: This is a precision frequency meter, such as the VHDL source code, which has a complete project file QuartusII.
Date : 2025-06-30 Size : 199kb User : 郑雄
Muliterfovhdl Downloaded：0: Muilter for vhdl
Date : 2025-06-30 Size : 291kb User : 小明
dds_9760_OK Downloaded：0: DDS signal source, for the use of VHDL. DIP switch which can be used to select the appropriate function: FM, ASK, PSK, AM (This is not to achieve good), but other well. Frequency of up to 25M
Date : 2025-06-30 Size : 4.86mb User : 李逵
cliff_cummings Downloaded：0: Useful papers on VHDL language by cliff cummings
Date : 2025-06-30 Size : 2.09mb User : 王静
SystemC-Tutorial Downloaded：0: systemc tutorial for ground up
Date : 2025-06-30 Size : 207kb User : rebecca
vhdl_slides Downloaded：0: vhdl
Date : 2025-06-30 Size : 546kb User : rebecca
my_uart_top Downloaded：0: To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and receive data. PC using the old tooth out of the se
Date : 2025-06-30 Size : 3kb User : 刘虎

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