VHDL-FPGA-Verilog List Page 3380

VHDL-FPGA-Verilog list

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chap7 Downloaded：0: Dozens of classic procedure, the structure described in the four-level with full-adder, a full-adder, using the conditional operator described in the four selected 1 MUX, etc.
Date : 2025-07-16 Size : 4kb User : chencong
chap9 Downloaded：0: With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
Date : 2025-07-16 Size : 7kb User : chencong
graphicallcd_latest.tar Downloaded：0: grapic automatically delete the directory of debug and directory of debug
Date : 2025-07-16 Size : 4kb User : Thuan
time Downloaded：0: Clock to achieve with digital stopwatch calendar set three alarm time, date, adjust
Date : 2025-07-16 Size : 2kb User : 楚辰
FINAL_OUT.VHD Downloaded：0: this is a vhdl program to test your LCD
Date : 2025-07-16 Size : 1kb User : sreeji
fre500000 Downloaded：0: Such as precision digital frequency meter Verilog source code, from top to bottom of design ideas, divided into six modules. Been to Altera' s FPGA boards. For your reference, hope you will not copy!
Date : 2025-07-16 Size : 2.82mb User : 程永生
upload Downloaded：0: Project 2 consists of three development boards for altera FPGA, the other for 51 boards. Function: TFT development. Contains the light test, and the OTP and so on.
Date : 2025-07-16 Size : 18.98mb User : jeny
v Downloaded：0: verilog code for a synthesizer based on Terasic s Multimedia development board. (MTDB) and Altera FPGA.
Date : 2025-07-16 Size : 35kb User : ahmadyan
lab4 Downloaded：0: vhdl uart lab ENTITY uart IS PORT ( SIGNAL clock,reset : IN STD_LOGIC SIGNAL sdatain : IN STD_LOGIC SIGNAL oready, sdataout : INOUT STD_LOGIC SIGNAL iready : INOUT STD_LOGIC SIGNAL charin : INOUT STD_LOGIC_VECTOR(7 DOWNT
Date : 2025-07-16 Size : 10kb User : work
shukongdianyabiao Downloaded：0: 51 MCU and LCD using the keyboard as a human-computer interaction, input you want to input voltage value, the port on the output of the corresponding binary number
Date : 2025-07-16 Size : 54kb User : 潘存华
spmem.tar Downloaded：0: Sinlge port RAM VHDL/Verilog design
Date : 2025-07-16 Size : 1kb User : Ravi
eeprom_i2c.tar Downloaded：0: I2C EEPROM verilog simulation model
Date : 2025-07-16 Size : 620kb User : Ravi

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