VHDL-FPGA-Verilog List Page 3375

VHDL-FPGA-Verilog list

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ripple_carry_counter Downloaded：0: verilog language into a simple 4-bit counter for the pulse, with the incentive simulation block
Date : 2025-07-21 Size : 389kb User : qirui
eda Downloaded：0: eda commonly used in experiments to the module, language VHDL
Date : 2025-07-21 Size : 88kb User : 闫更辉
FPGA Downloaded：0: Getting Started with FPGA Series tutorials for beginners, very practical.
Date : 2025-07-21 Size : 9.1mb User : 闫更辉
calculator Downloaded：1: Using VHDL in quartus2 achieve calculator. Input 4* 4 matrix keyboard, the output data lines for sharing of digital control. Can achieve a simple mathematical operations, logical operations, binary conversion, continuous
Date : 2025-07-21 Size : 1.22mb User : jizhen
seg Downloaded：0: Written in VHDL, digital tube display program (digital control shared data line), with a binary conversion
Date : 2025-07-21 Size : 698kb User : jizhen
car Downloaded：0: Implemented using VHDL infrared tracking car program, using eight infrared diodes (mounted on the front of the bottom) to identify traffic, then L298 motor driver circuit, be able to run a white background, black track,
Date : 2025-07-21 Size : 629kb User : jizhen
VHDL_FINAL Downloaded：0: Attached file has a detailed description of source code and input and output, including analog graphics and flow charts
Date : 2025-07-21 Size : 1.98mb User : 呂偉民
Bch15_5 Downloaded：0: The attached file consists of implimentation of BCH codes in VHDL programming using XILINX software. This code will reduce the no. of gates requirement.
Date : 2025-07-21 Size : 13kb User : babi
verilog_cordic_core_latest.tar Downloaded：0: hi this verilog code for library
Date : 2025-07-21 Size : 355kb User : praveen
timercounter-8253-programmable-using-VHDL Downloaded：1: implementation of IC5283
Date : 2025-07-21 Size : 388kb User : SATYA
A-IMPLEMENTATION-OF-TELEMETRY Downloaded：0: Implementation of telemetry link
Date : 2025-07-21 Size : 504kb User : SATYA
LCD Downloaded：0: module lcd_driver(clk,rst,LCD_DATA,RS,RW,EN) input clk,rst //rst is the signal of reset,active low(0). output RS,RW,EN //RS=0 时为写指令；RS=1 时为写数据 //RW=0 时对 LCD 模块执行写操作； //RW=1 时对 LCD 模块执行读操作 //EN 为 LCD 模块的使能信号（下降沿触发） output
Date : 2025-07-21 Size : 857kb User : 翁俊杰

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