VHDL-FPGA-Verilog List Page 3385

VHDL-FPGA-Verilog list

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modelsim_6.3f_6.4b_6.5_crck Downloaded：0: modelsim se 6.3f 6.4b 6.5
Date : 2025-07-22 Size : 301kb User : yanghong
altera_avalon_i2c_V90 Downloaded：0: I2C IP for Quartus V9.0, can used in SOPC builder.
Date : 2025-07-22 Size : 12kb User : homeuser
altera_avalon_i2c_V91 Downloaded：0: I2C IP for Quartus V9.0, can used in SOPC builder.
Date : 2025-07-22 Size : 12kb User : homeuser
oc_i2c_master_top_v92 Downloaded：0: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Date : 2025-07-22 Size : 3kb User : homeuser
oc_i2c_master_v92 Downloaded：0: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Date : 2025-07-22 Size : 1kb User : homeuser
oc_i2c_master_byte_ctrl_v92 Downloaded：0: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Date : 2025-07-22 Size : 3kb User : homeuser
oc_i2c_master_bit_ctrl_v92 Downloaded：0: I2C IP for Quartus V9.0 sp2, can used in SOPC builder.
Date : 2025-07-22 Size : 4kb User : homeuser
PetervrlK_verilog Downloaded：0: Verilog Introduction , a general summary of syntax and structure of Verilog language !
Date : 2025-07-22 Size : 112kb User : Danh
ps2_DE1_HEX Downloaded：0: Display Scancode of PS2 on DE1 board !
Date : 2025-07-22 Size : 377kb User : Danh
buzzer Downloaded：0: Buzzer to give written using Verilog HDL output ' duo, Lai ... ...' tone of the program
Date : 2025-07-22 Size : 436kb User : 刘月
cf_dpsk Downloaded：0: VHDl written in a language with DPSK modulation and demodulation process, the program can be achieved relative phase modulation and demodulation. Can be run on xilinx ISE or QuartusII next.
Date : 2025-07-22 Size : 728kb User : 周
viterbidecoder Downloaded：0: viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
Date : 2025-07-22 Size : 5kb User : zhouli

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