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VHDL-FPGA-Verilog list
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TDvedynausermanual
Downloaded:0
ve-DYNA ® provides users with vehicle dynamics, nonlinear behavior can be configured vehicle simulation model. Users according to their engineering problems select the appropriate models (cars, trucks, trailers) and
Date
: 2025-11-19
Size
: 4.05mb
User
:
dd
VHDLdepinlvji
Downloaded:0
基于VHDL的频率计设计 很好用的 希望要用的同志来下载
Date
: 2025-11-19
Size
: 160kb
User
:
李华
wannianlizhizuo
Downloaded:0
基于vhdl的万年历制作
Date
: 2025-11-19
Size
: 1.17mb
User
:
李华
dianticontrol
Downloaded:0
This source of FPGA-based VERILOG elevator control procedures.
Date
: 2025-11-19
Size
: 10kb
User
:
王强
flash
Downloaded:0
The source code for the FPGA-based FLASH memory using the VERILOG prepared to read and write procedures.
Date
: 2025-11-19
Size
: 198kb
User
:
王强
I2C
Downloaded:0
The source code for the FPGA-based implementation of I2C bus protocol of the program, the program is implemented to read and write AT24C02 chip.
Date
: 2025-11-19
Size
: 71kb
User
:
王强
en_ctrl(u)
Downloaded:0
The source code for the FPGA-based LCD screen display digital clock program, the program includes a powerful liquid crystal display control module.
Date
: 2025-11-19
Size
: 162kb
User
:
王强
DE0_LTMLCD
Downloaded:0
Supporting the development board altera company DE0 the demo of a simple DE0
Date
: 2025-11-19
Size
: 117kb
User
:
TaoLi
source
Downloaded:0
A basic DMA Controller source code
Date
: 2025-11-19
Size
: 15kb
User
:
cadu903
VGA_Controller
Downloaded:0
output video from VGA port easily!
Date
: 2025-11-19
Size
: 1kb
User
:
张坤
programtested7.27
Downloaded:0
Channel estimation can be integrated module, including the solution OFDM, pilot solution for the 8x8, 2048 points of OFDM signals in channel estimation
Date
: 2025-11-19
Size
: 6kb
User
:
赵剑雄
Cyclone_II_FPGA_Minimum_System
Downloaded:0
Minimum System Cyclone II FPGA circuit connections. Configuration and PLL configuration contains JETAG
Date
: 2025-11-19
Size
: 83kb
User
:
shenyiqun
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