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LinPF_RLS
Downloaded:0
VHDL code for linear prediction filter based on RLS (recursive least square). Filter order is set to 4, bit precision set to 12 bits for input and output. Signals are complex signals.
Date
: 2025-11-21
Size
: 5kb
User
:
徐滨
QAM16_demo
Downloaded:0
This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.
Date
: 2025-11-21
Size
: 44kb
User
:
徐滨
ipv4_packet_transmitter_latest.tar
Downloaded:0
VHDL ethernet implementation on a FPGA
Date
: 2025-11-21
Size
: 25kb
User
:
gabymour
spi_test
Downloaded:0
VHDL ethernet implementation on FPGA
Date
: 2025-11-21
Size
: 273kb
User
:
gabymour
verilog
Downloaded:0
File contains the register, shift register, may counter, counter, implemented with the VHDL modules.
Date
: 2025-11-21
Size
: 4kb
User
:
朱向南
EX2
Downloaded:0
nios ii embedded digital control implementation (key switch), LCD time display
Date
: 2025-11-21
Size
: 5.3mb
User
:
feipan
ic7
Downloaded:0
Functions with odd parity of serial data transmission circuit, with the state machine implementation.
Date
: 2025-11-21
Size
: 1kb
User
:
天天
clk
Downloaded:0
Program for digital date display (buttons can control the day, hours, minutes and seconds to switch) and LCD display
Date
: 2025-11-21
Size
: 2kb
User
:
feipan
XilinxFPGA(1-60)
Downloaded:0
Systematically describes the development of Xilinx FPGA knowledge, including Introduction to FPGA development, Verilog HDL language based on chip-based Xilinx HDL Language Advanced Advanced, ISEd development environment,
Date
: 2025-11-21
Size
: 12.18mb
User
:
xincheng
LogicLock
Downloaded:0
Digital mixer, verilog and mixed programming schematic
Date
: 2025-11-21
Size
: 3.45mb
User
:
张旭
IEEE.Standard.Verilog.Hardware.Description.Languag
Downloaded:0
IEEE Standard Verilog Hardware Description Language(
Date
: 2025-11-21
Size
: 2.08mb
User
:
liukai
DDSSYNCtrl_tri_face
Downloaded:0
AD9910 experimental code, the use of parallel fast FM, the programming language through the schematic and mixed
Date
: 2025-11-21
Size
: 16.2mb
User
:
张旭
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