VHDL-FPGA-Verilog List Page 2759

VHDL-FPGA-Verilog list

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5 Downloaded：0: Based on the HDB3 Encoder SYSTEMVIEW experimental design and see for yourself
Date : 2025-11-21 Size : 206kb User : 张证验
i2c Downloaded：0: I2C verilog RTL code， support master and slave mode
Date : 2025-11-21 Size : 13kb User : dingyy
mdio Downloaded：0: MDIO verilog RTL code
Date : 2025-11-21 Size : 4kb User : dingyy
LEON2_Nocache Downloaded：0: It is a modified version of LEON2 VHDL code. The cache units are removed in this version.
Date : 2025-11-21 Size : 458kb User : hamed
VHDLguoliangjiance Downloaded：0: Zero-crossing detection, the output part of the integer part and offset a part
Date : 2025-11-21 Size : 673kb User : liutao
ModelSim2 Downloaded：0: Logic analysis tools using Modelsim tutorial, this is the second part of the
Date : 2025-11-21 Size : 190kb User : liutao
CLK_DIV Downloaded：0: Used to generate a reference clock signal circuit and can produce this as a reference clock signal into the other and the clock multiplier
Date : 2025-11-21 Size : 1kb User : da
bin2bcd Downloaded：0: To the binary signal into BCD code in the form of signals, used in the digital display the corresponding number.
Date : 2025-11-21 Size : 247kb User : da
generator Downloaded：0: Signal generator, used to generate the required input and output signals corresponding to the signal.
Date : 2025-11-21 Size : 352kb User : da
lab4showTAs Downloaded：0: 4 seg display, button debouncer, and controller for parking meter
Date : 2025-11-21 Size : 711kb User : notjustcarbon
KTMTNC Downloaded：0: 5 lab organization computer
Date : 2025-11-21 Size : 4.02mb User : le
SOPC_SOURCE_PROGRAM Downloaded：0: fpga variety of source, C form. Include: lcd, led, ps2, jtag and so on.
Date : 2025-11-21 Size : 183kb User : likun

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