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VHDL-FPGA-Verilog list
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Fpga board verilog write serial port to send data module, the main can look at ideas, is also available
Date : 2025-05-28 Size : 1kb User : 徐林

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Carried out between the DSP and the FPGA XINTF asynchronous communication functions, debugging, and stable operation
Date : 2025-05-28 Size : 5.39mb User : 刘帅

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Based VHDL design Gray Gray code encoder (Gray) code is a reliability of the encoder, it has been widely used in digital systems
Date : 2025-05-28 Size : 3kb User : 贺泽伟

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Including synchronous and asynchronous clear to enable the addition counter binary counter is the most widely used one of the most versatile counter with asynchronous clear and specific work process synchronization enabl
Date : 2025-05-28 Size : 3kb User : 贺泽伟

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Dynamic eight seven-segment LED display circuit design uses two one four, 7-segment LED common learning CASE statement VHDL design methods and the multi-level
Date : 2025-05-28 Size : 3kb User : 贺泽伟

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NC divider d esign feature is that when the given input different input data, the frequency divider with a different frequency division ratio of the input clock signal, the count value NC divider is parallel preset addin
Date : 2025-05-28 Size : 3kb User : 贺泽伟

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Use verilog to achieve run time function
Date : 2025-05-28 Size : 16.32mb User : yang

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Simple Arinc-429 transmitter channel description on Verilog HDL with parameterized DATA FIFO.
Date : 2025-05-28 Size : 4kb User : scnn86

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Simple SPI interface realization on Verilog HDL with parameterized FIFO and APB interface
Date : 2025-05-28 Size : 11kb User : scnn86

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Simple realization of I2C interface on System Verilog HDL with support of interrupt generation.
Date : 2025-05-28 Size : 6kb User : scnn86

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Sipmle external bus controller realization on Verilog HDL with AHB interface. Support RAM/ROM/NAND Flash devices.
Date : 2025-05-28 Size : 10kb User : scnn86

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Simple 32-bit timer realization with APB interface with support of interrupt generation and switching clock source.
Date : 2025-05-28 Size : 3kb User : scnn86
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