VHDL-FPGA-Verilog List Page 270

VHDL-FPGA-Verilog list

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_MATLAB_AND_FPGA_AlteraVerilog Downloaded：0: U6570 u5B57 u901A u4FE1 u540C u6B65 u6280 u672F u7684MATLAB u4E0EFPGA u5B9E u73B0 Altera/Verilog u7248
Date : 2025-05-26 Size : 48.55mb User : 不严重
DDS_BPSK Downloaded：0: U57FA u4E8.08 u868
Date : 2025-05-26 Size : 43.71mb User : 不言中
DDS Downloaded：0: Four channel DDS signal generator
Date : 2025-05-26 Size : 566kb User : 王勇
EDA Downloaded：0: Familiar with Quartus II Verilog HDL text design process, learning counter design, simulation and hardware testing.
Date : 2025-05-26 Size : 30.81mb User : 小麻
shift_reg_control Downloaded：0: vivado project for shift register in vhdl
Date : 2025-05-26 Size : 87kb User : sandeepthi
interpolation Downloaded：0: vivado project file for down scaling of image by scale factor 2
Date : 2025-05-26 Size : 28.08mb User : sandeepthi
dianti Downloaded：1: dianti in verilog
Date : 2025-05-26 Size : 726kb User : 邓奇
fpga_video_game-master Downloaded：0: Helicopter game in verilog
Date : 2025-05-26 Size : 21.86mb User : 邓奇
ram Downloaded：0: RAM chip based on VHDL continuous read and write
Date : 2025-05-26 Size : 1kb User : 9999
pcie_sg_dma_latest.tar Downloaded：0: vhdl for dma
Date : 2025-05-26 Size : 39.78mb User : 姜晓明
C430 Downloaded：0: Core visual C4-30 development board self start code, which has Audio_wm, DDR, LCD, PS2, VGA, and many other self inspection procedures
Date : 2025-05-26 Size : 569kb User : 程竹
Implement-a-CPU Downloaded：0: Implement a CPU which supports a subset of MIPS operations using Verilog HDL on FPGA Xilinx Basys 3
Date : 2025-05-26 Size : 2.97mb User : 骆扬

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