VHDL-FPGA-Verilog List Page 2547

VHDL-FPGA-Verilog list

Sort by ：

« 1 2 ... .42 .43 .44 .45 .46 2547.48 .49 .50 .51 .52 ... 4310 »

VerilogHDL_Synthesis Downloaded：0: VerilogHDL_Synthesis_A_Practical_Primer, a classic verilog tutorial introduces synthesizable verilog, very helpful for the hardware to do
Date : 2025-11-22 Size : 4.75mb User : 曾健林
limit_vhdl Downloaded：0: pid control clipping part of the period, as well as positional pid code. Down on the extract from the reference
Date : 2025-11-22 Size : 3.2mb User : 刘大仔
phone Downloaded：0: Imitation of dial-up, and there are number of transistors display input
Date : 2025-11-22 Size : 1kb User : jiangyan
FSM Downloaded：0: Finite state machine is refers to the output depends on the past input part and the current input portion of temporal logic circuit. Generally speaking, besides input part and output part outside, finite state machine st
Date : 2025-11-22 Size : 1kb User : 李小明
mult4x4 Downloaded：0: CLK: standard clock signal, in this case, the frequency for 4Hz Clk_1k: produce make businessis about to strike the sound of the clock signal, in this example, the frequency for 1024Hz Can only read prior stored data of
Date : 2025-11-22 Size : 1kb User : 李小明
sell Downloaded：0: CLK: standard clock signal, in this case, the frequency for 4Hz Now, the vending machine industry is on her way to the information and further achieve rationalization. For example implements online mode, through telephon
Date : 2025-11-22 Size : 1kb User : 李小明
shiyanshu Downloaded：0: VHDL language test for the beginner series, personally think very helpful for beginners.
Date : 2025-11-22 Size : 1.28mb User : zuoya
SPI_system Downloaded：0: This is a SPI for DE_2 board.The file sampling frequency is 20Khz and board frequency used by this 27Mhz.The slaver chip is MCP2302 working under 3.3V.Finally the input analogue voltage for CH0 is between 0V and 3.3V.The
Date : 2025-11-22 Size : 1.6mb User : wei chenghao
ass1_2_hamming Downloaded：0: a) Develop a Verilog module that will generate a 7-bit encoded data from a 4-bit data. Simulate your design for two inputs. Use even or odd parity according to the least significant figure of your ID number. b) Develop a
Date : 2025-11-22 Size : 1.08mb User : wei chenghao
ass1_3_safe Downloaded：0: The objective of this assignment is to design and implement the controller for an electronic safe. You will interface a 16-button keypad to the NIOS boards. The combination code of the safe will be the last “X” digits of
Date : 2025-11-22 Size : 1.3mb User : wei chenghao
gap_finder Downloaded：0: Design a sequential machine that finds the size of the largest gap between two successive 1s in a X-bit word. Partition the design into a state machine controller and a datapath. The datapath accepts the X-bit word and p
Date : 2025-11-22 Size : 557kb User : wei chenghao
CPU Downloaded：0: cup developed by scope verilog
Date : 2025-11-22 Size : 9kb User : wei chenghao

« 1 2 ... .42 .43 .44 .45 .46 2547.48 .49 .50 .51 .52 ... 4310 »

Search in result