This is a SPI for DE_2 board.The file sampling frequency is 20Khz and board frequency used by this 27Mhz.The slaver chip is MCP2302 working under 3.3V.Finally the input analogue voltage for CH0 is between 0V and 3.3V.The specific report is also included in it

SPI_assigment.docx
Verilog demonstation\clock_divider\clock_divider.asm.rpt
....................\.............\clock_divider.done
....................\.............\clock_divider.fit.rpt
....................\.............\clock_divider.fit.summary
....................\.............\clock_divider.flow.rpt
....................\.............\clock_divider.map.rpt
....................\.............\clock_divider.map.summary
....................\.............\clock_divider.pin
....................\.............\clock_divider.pof
....................\.............\clock_divider.qpf
....................\.............\clock_divider.qsf
....................\.............\clock_divider.qws
....................\.............\clock_divider.sim.rpt
....................\.............\clock_divider.sof
....................\.............\clock_divider.tan.rpt
....................\.............\clock_divider.tan.summary
....................\.............\clock_divider.v
....................\.............\clock_divider.v.bak
....................\.............\clock_divider.vwf
....................\.............\db\clock_divider.asm.qmsg
....................\.............\..\clock_divider.asm.rdb
....................\.............\..\clock_divider.asm_labs.ddb
....................\.............\..\clock_divider.cbx.xml
....................\.............\..\clock_divider.cmp.bpm
....................\.............\..\clock_divider.cmp.cdb
....................\.............\..\clock_divider.cmp.ecobp
....................\.............\..\clock_divider.cmp.hdb
....................\.............\..\clock_divider.cmp.kpt
....................\.............\..\clock_divider.cmp.logdb
....................\.............\..\clock_divider.cmp.rdb
....................\.............\..\clock_divider.cmp.tdb
....................\.............\..\clock_divider.cmp0.ddb
....................\.............\..\clock_divider.cmp_merge.kpt
....................\.............\..\clock_divider.db_info
....................\.............\..\clock_divider.eco.cdb
....................\.............\..\clock_divider.eds_overflow
....................\.............\..\clock_divider.fit.qmsg
....................\.............\..\clock_divider.hier_info
....................\.............\..\clock_divider.hif
....................\.............\..\clock_divider.lpc.html
....................\.............\..\clock_divider.lpc.rdb
....................\.............\..\clock_divider.lpc.txt
....................\.............\..\clock_divider.map.bpm
....................\.............\..\clock_divider.map.cdb
....................\.............\..\clock_divider.map.ecobp
....................\.............\..\clock_divider.map.hdb
....................\.............\..\clock_divider.map.kpt
....................\.............\..\clock_divider.map.logdb
....................\.............\..\clock_divider.map.qmsg
....................\.............\..\clock_divider.map_bb.cdb
....................\.............\..\clock_divider.map_bb.hdb
....................\.............\..\clock_divider.map_bb.logdb
....................\.............\..\clock_divider.pre_map.cdb
....................\.............\..\clock_divider.pre_map.hdb
....................\.............\..\clock_divider.rtlv.hdb
....................\.............\..\clock_divider.rtlv_sg.cdb
....................\.............\..\clock_divider.rtlv_sg_swap.cdb
....................\.............\..\clock_divider.sgdiff.cdb
....................\.............\..\clock_divider.sgdiff.hdb
....................\.............\..\clock_divider.sim.cvwf
....................\.............\..\clock_divider.sim.hdb
....................\.............\..\clock_divider.sim.qmsg
....................\.............\..\clock_divider.sim.rdb
....................\.............\..\clock_divider.sld_design_entry.sci
....................\.............\..\clock_divider.sld_design_entry_dsc.sci
....................\.............\..\clock_divider.smart_action.txt
....................\.............\..\clock_divider.smp_dump.txt
....................\.......

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