VHDL-FPGA-Verilog List Page 2544

VHDL-FPGA-Verilog list

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mult Downloaded：0: used for multiplexing
Date : 2025-11-22 Size : 1kb User : cyril
32bitCLA Downloaded：0: a carry look ahead adder
Date : 2025-11-22 Size : 1kb User : cyril
traffc_lght Downloaded：0: my project code of traffic light controller in vhdl
Date : 2025-11-22 Size : 308kb User : divya
MA_HOA_MANCHESTER Downloaded：0: MANCHESTER ENCODING IN VHDL
Date : 2025-11-22 Size : 1kb User : nguyen
state-machine Downloaded：0: State machine, one-hot code experiment, a simple Verilog language design For NJU, simple
Date : 2025-11-22 Size : 566kb User : 戴连鹏
Timer Downloaded：0: The design of the timer, run by the Quartus II, FOR NJU Cser. Used signaltap
Date : 2025-11-22 Size : 1.84mb User : 戴连鹏
Counter Downloaded：0: The design of the timer, run by the Quartus II, easy to use, mainly For NJU CSers
Date : 2025-11-22 Size : 805kb User : 戴连鹏
I2C_Verilog_Model Downloaded：0: This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
Date : 2025-11-22 Size : 356kb User : jinjin
SD_Controller_Verilog Downloaded：0: This source package is the SD card and MMC card controler model based on the Verilog language. It has the following 4 parts: RTL language, testbench, software simulating files and help document.
Date : 2025-11-22 Size : 1.58mb User : jinjin
fpga Downloaded：0: FPGA-based signal modulation, can produce sine wave, and the ASK modulation and AM modulation
Date : 2025-11-22 Size : 7kb User : 张沐松
sirenqiangdaqi Downloaded：0: 4 participants to design a quiz answer in timer. Time control circuit has functions to answer questions.
Date : 2025-11-22 Size : 6kb User :
Final Downloaded：0: This module contains a digital clock which can enables clock setup option and up to four alarms. This was targeted Virtex-5 FPGA (ML501) and interfaced with LCD display. and center, north and east push buttons.
Date : 2025-11-22 Size : 1.04mb User : mvnvprasad

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