VHDL-FPGA-Verilog List Page 2489

VHDL-FPGA-Verilog list

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Embedded-Processor-Block Downloaded：0: This reference guide is a description of the embedded processor block in Virtex® -5 FXT FPGAs.
Date : 2025-11-22 Size : 2.53mb User : zhang
decrypt_controll Downloaded：0: controller for fast_aes128. Sends start and load pulses at a lower clock than main_clk.
Date : 2025-11-22 Size : 1kb User : safe_cpu
downsizer Downloaded：0: A FSM that extracts the 18 LSB out of a 128 bit vector and forwards it as a 18 bit vector.
Date : 2025-11-22 Size : 1kb User : safe_cpu
freqdiv Downloaded：0: A frequenzzzy divider that divides the clock signal rate with a factor of 25.
Date : 2025-11-22 Size : 1kb User : safe_cpu
IO_controll Downloaded：0: this is a controller, mainly for the nexys2 board based around the spartan 3E fpga from xilinx. controlls various outputs and inputs.
Date : 2025-11-22 Size : 1kb User : safe_cpu
stoppsignal Downloaded：0: A VHDL module that counts long pulses on the inport counting rising edges.
Date : 2025-11-22 Size : 1kb User : safe_cpu
mc_t Downloaded：0: Verilog implementation using H.264 in the half-pixel interpolation function. 30 cycles to complete a 4x4 pieces of horizontal, vertical and diagonal interpolation.
Date : 2025-11-22 Size : 16.5mb User : 吴汶泰
mc Downloaded：0: H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.
Date : 2025-11-22 Size : 405kb User : 吴汶泰
DM9000A Downloaded：0: About DM9000A development, use NIosII software, alteraFPGA examples of design
Date : 2025-11-22 Size : 1.84mb User : 杨晓飞
bei Downloaded：0: Applications written in VHDL multiplier, high-frequency signals through low frequency signal divided by the frequency
Date : 2025-11-22 Size : 1kb User : 胡佳
clk_div Downloaded：0: deviseur de fréquence pour fpga
Date : 2025-11-22 Size : 1kb User : thami
counter Downloaded：0: counter design in vhdl
Date : 2025-11-22 Size : 1kb User : rukan

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