H.264 algorithm by VHDL implementation of the half pixel interpolation module. The module can be in 30 children complete a cycle of vertical and horizontal 4x4 block Xiecha value.

mc\iseconfig\mc.projectmgr
..\.........\mc.xreport
..\mc.gise
..\mc.vhd
..\mc.wcfg
..\mc.xise
..\mc_bitgen.xwbt
..\mc_guide.ncd
..\mc_summary.html
..\mc_tb.vhd
..\mc_tb_isim_beh1.wdb
..\pepExtractor.prj
..\_xmsgs\netgen.xmsgs
..\ipcore_dir
..\iseconfig
..\templates
..\_xmsgs
mc

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