About DM9000A development, use NIosII software, alteraFPGA examples of design

DE2_NET\.metadata\.lock
.......\.........\.log
.......\.........\.plugins\org.eclipse.cdt.core\.log
.......\.........\........\................make.core\specs.c
.......\.........\........\.........................\specs.cpp
.......\.........\........\.....................ui\dialog_settings.xml
.......\.........\........\.............ore.resources\.root\.indexes\history.version
.......\.........\........\..........................\.....\........\properties.version
.......\.........\........\..........................\.....\1.tree
.......\.........\........\..........................\.safetable\org.eclipse.core.resources
.......\.........\........\..................untime\.settings\org.eclipse.cdt.debug.core.prefs
.......\.........\........\........................\.........\org.eclipse.cdt.ui.prefs
.......\.........\........\........................\.........\org.eclipse.core.resources.prefs
.......\.........\........\........................\.........\org.eclipse.ui.ide.prefs
.......\.........\........\........................\.........\org.eclipse.ui.prefs
.......\.........\........\............ui.ide\dialog_settings.xml
.......\.........\........\...............workbench\dialog_settings.xml
.......\.........\........\........................\workbench.xml
.......\.........\version.ini
.......\.sopc_builder\install.ptf
.......\.............\install2.ptf
.......\.............\preferences.xml
.......\altpllpll_0.ppf
.......\Audio_0.v
.......\AUDIO_DAC_FIFO.v
.......\Audio_PLL.ppf
.......\Audio_PLL.v
.......\bht_ram.mif
.......\button_pio.v
.......\clock_0.v
.......\clock_1.v
.......\cpu_0.ocp
.......\cpu_0.v
.......\cpu_0.vo
.......\cpu_0_bht_ram.mif
.......\cpu_0_dc_tag_ram.mif
.......\cpu_0_ic_tag_ram.mif
.......\cpu_0_jtag_debug_module.v
.......\cpu_0_jtag_debug_module_wrapper.v
.......\cpu_0_mult_cell.v
.......\cpu_0_ociram_default_contents.mif
.......\cpu_0_rf_ram_a.mif
.......\cpu_0_rf_ram_b.mif
.......\cpu_0_test_bench.v
.......\dc_tag_ram.mif
.......\DE2_NET.asm.rpt
.......\DE2_NET.bsf
.......\DE2_NET.done
.......\DE2_NET.dpf
.......\DE2_NET.fit.rpt
.......\DE2_NET.fit.smsg
.......\DE2_NET.fit.summary
.......\DE2_NET.flow.rpt
.......\DE2_NET.jdi
.......\DE2_NET.map.rpt
.......\DE2_NET.map.smsg
.......\DE2_NET.map.summary
.......\DE2_NET.pin
.......\DE2_NET.pof
.......\DE2_NET.qpf
.......\DE2_NET.qsf
.......\DE2_NET.qws
.......\DE2_NET.sof
.......\DE2_NET.tan.rpt
.......\DE2_NET.tan.summary
.......\DE2_NET.v
.......\DE2_NET.v.bak
.......\DE2_NET_assignment_defaults.qdf
.......\.M9000A\cb_generator.pl
.......\.......\class.ptf
.......\.......\hdl\DM9000A_IF.v
.......\.......\inc\basic_io.h
.......\.......\...\DM9000A.C
.......\.......\...\DM9000A.H
.......\DM9000A.v
.......\DM9000A_IF.v
.......\EP2C35_NET.bdf
.......\epcs_controller.v
.......\epcs_controller_boot_rom.hex
.......\FIFO_16_256.v
.......\I2C_AV_Config.v
.......\I2C_Controller.v
.......\ic_tag_ram.mif
.......\Img_DATA.hex
.......\Img_RAM.v
.......\ISP1362.v
.......\ISP1362_IF.v
.......\jtag_uart_0.v
.......\lcd_16207_0.v
.......\led_green.v
.......\led_red.v
.......\README.txt
.......\Reset_Delay.v
.......\rf_ram_a.mif
.......\rf_ram_b.mif
.......\sdram_0.v
.......\sdram_0_test_component.v
.......\SDRAM_PLL.ppf
.......\SDRAM_PLL.v
.......\SD_CLK.v

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