VHDL-FPGA-Verilog List Page 2467

VHDL-FPGA-Verilog list

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hw1 Downloaded：0: Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behav
Date : 2025-11-23 Size : 357kb User : vinay
hw2 Downloaded：0: Using the VHDL Entry Method, design a logic circuit that behaves as a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borro
Date : 2025-11-23 Size : 613kb User : vinay
hw3 Downloaded：0: Write VHDL codes to model an 8-bit counter that counts every second. It counts from your last two digits of your student ID to your next two digits of your student ID. If the last two digits are greater than the next two
Date : 2025-11-23 Size : 344kb User : vinay
hw5 Downloaded：0: Design a 2-digit stopwatch that ticks every second. A switch is used to start and stop the time. When the switch is pushed, the time will start and when it is pushed again, the time will stop. In order for the switch to
Date : 2025-11-23 Size : 1.31mb User : vinay
hw4 Downloaded：0: Write VHDL codes to show, on two 7-segment LEDs, the binary coded decimal (BCD) equivalence of the binary representation of the state of eight switches. Use a function to perform the specified task. Assume that the 7-seg
Date : 2025-11-23 Size : 324kb User : vinay
reg-a-wire Downloaded：0: verilog using the difference between reg and wire and method of use
Date : 2025-11-23 Size : 2kb User : 张树强
main Downloaded：0: FPGA-based Nokia 3310 display driver drivers to simulate SPI Transfer Mode
Date : 2025-11-23 Size : 1kb User : 吕念
ad706_7276 Downloaded：0: DA7276 of the verilog code, timing still accurate, can be directly copied using
Date : 2025-11-23 Size : 42kb User : huangying
seg7led Downloaded：0: quartus 2 html language seven sections of pipe
Date : 2025-11-23 Size : 1kb User : 陈涛
ledwatertest Downloaded：0: Written in a flowing light with verilog program more useful for beginners, mainly for the understanding of the state machine transition.
Date : 2025-11-23 Size : 35kb User : huangying
fpga Downloaded：0: Including fpga so the procedure is a very good learning materials
Date : 2025-11-23 Size : 7.62mb User : liuyanan
risc8 Downloaded：0: 8 bit risc code with verilog
Date : 2025-11-23 Size : 49kb User : richard

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