Introduction - If you have any usage issues, please Google them yourself
Using the VHDL Entry Method, design a logic circuit that behaves as a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in when the control input SubAddn is ‘1’.