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VHDL-FPGA-Verilog list
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decoder
Downloaded:0
this is the code for decoder in verilog
Date
: 2025-11-23
Size
: 217kb
User
:
Muhammad Kamran
traffic-light
Downloaded:0
The design of a traffic control light for the intersection, a countdown function, Verilog language, Quratus II compile.
Date
: 2025-11-23
Size
: 540kb
User
:
姜涛
Example-6-1
Downloaded:0
Write state machine 1.Example-6-1 \ FSM \ state1 directory for a description method of source-type FSM 2.Example-6-1 \ FSM \ state2 directory FSM description method for the two-stage source 3.Example-6-1 \ FSM \ state3 d
Date
: 2025-11-23
Size
: 72kb
User
:
林立
Example-5-8
Downloaded:0
Extended Operations Shannon Shannon expansion of Boolean logic or extension, is simply the reverse Carnot logical operations. Shannon expansion is equivalent to the logical replication, increased frequency and simplifica
Date
: 2025-11-23
Size
: 39kb
User
:
林立
shifter
Downloaded:0
With arithmetic shift and logical shift, rotate functions shift register, Verilog language, Quratus II compile.
Date
: 2025-11-23
Size
: 292kb
User
:
姜涛
Counter
Downloaded:0
Verilog language with 74* 163 counters, Quratus II compiled by
Date
: 2025-11-23
Size
: 275kb
User
:
姜涛
Register
Downloaded:0
verilog implementation of a 32-byte 8-bit memory block, Quratus II compile.
Date
: 2025-11-23
Size
: 932kb
User
:
姜涛
uart
Downloaded:0
verilog uart prepared to send and receive the source code. Straightforward.
Date
: 2025-11-23
Size
: 468kb
User
:
luoqv
270CPLD
Downloaded:0
pxa270 s cpld
Date
: 2025-11-23
Size
: 134kb
User
:
golfer
lcd1602
Downloaded:0
verilog source code written LCD1602 control, can display a string of characters.
Date
: 2025-11-23
Size
: 663kb
User
:
luoqv
sdram_mdl
Downloaded:0
verilog SDRAM write control of the source code, development FPGA/CPLD
Date
: 2025-11-23
Size
: 2.18mb
User
:
luoqv
uartfifo
Downloaded:0
FPGA-based serial port source code, a string can be sent through the FIFO.
Date
: 2025-11-23
Size
: 821kb
User
:
luoqv
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.52
.53
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.55
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.59
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.61
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4310
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