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VHDL-FPGA-Verilog list
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syn_fifo
Downloaded:0
Synchronous (single clock) FIFO,using SystemVerilog
Date
: 2025-11-23
Size
: 1kb
User
:
张三
ram_sp_sr_sw
Downloaded:0
Synchronous read write RAM, using systemverilog
Date
: 2025-11-23
Size
: 1kb
User
:
张三
DCT_watermark
Downloaded:0
Discrete Fourier Transform-based watermarking algorithm PSNR
Date
: 2025-11-23
Size
: 511kb
User
:
sanga
LCD1602_ysd
Downloaded:0
LCD1602 program code, through the development board validation, correct use of Verilog language
Date
: 2025-11-23
Size
: 2.2mb
User
:
王红
RS232_ysd
Downloaded:0
RS232 serial communication program, through the development board verification, the program is correct, is written using Verilog
Date
: 2025-11-23
Size
: 1.29mb
User
:
王红
state-machine-
Downloaded:0
VHDL state machine of the source language to help learn the language of the state machine VHDL
Date
: 2025-11-23
Size
: 4kb
User
:
f_add
Downloaded:0
EDA test full adder in VHDL language implementation, including the half adder, full adder, JK flip-flop, D flip-flop and the frequency of the source 50m
Date
: 2025-11-23
Size
: 1.26mb
User
:
xulie
Downloaded:0
EDA test sequence generator in VHDL, including source code, simulation waveforms
Date
: 2025-11-23
Size
: 606kb
User
:
motor-positioning-control-vhdl
Downloaded:0
Stepper motor positioning control system and simulation of VHDL program, absolutely can, after I completed the test set!
Date
: 2025-11-23
Size
: 1kb
User
:
卡卡
DIGITAL_SONG
Downloaded:0
Buzzer frequency control using FPGA music playback simple music player.
Date
: 2025-11-23
Size
: 68kb
User
:
Him
H2C35-V6-core
Downloaded:0
FPGA development board schematics, core board, EP2C series, we want to help
Date
: 2025-11-23
Size
: 150kb
User
:
黄石唯
TX
Downloaded:0
In data transmission and telecommunication, bit stuffing (also known—uncommonly—as positive justification) is the insertion of noninformation bits into data. Stuffed bits should not be confused with overhead bits. Bit st
Date
: 2025-11-23
Size
: 2.32mb
User
:
lep
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.81
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.83
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2385
.86
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4310
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