VHDL-FPGA-Verilog List Page 2323

VHDL-FPGA-Verilog list

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Exp12_LCD_Test Downloaded：0: In the Nios II in the design of liquid crystal display LCD
Date : 2025-11-23 Size : 2.35mb User : 晏翊
Exp24_Spectrum_Analyzer Downloaded：0: NIOS II FPGA and the design based on a spectrum analyzer
Date : 2025-11-23 Size : 10.25mb User : 晏翊
Exp25_USB_Reader Downloaded：0: Nios II FPGA-based design with USB electronic text reader
Date : 2025-11-23 Size : 9.89mb User : 晏翊
RS232 Downloaded：0: VHDL hardware description language used for serial communication interface circuit design, through the RS232 protocol to communicate with the PC unit.
Date : 2025-11-23 Size : 767kb User : tanzhde
up-down-counter Downloaded：0: up down counter by verilog
Date : 2025-11-23 Size : 658kb User : nedved
digital-clock Downloaded：0: digital clock by verilog
Date : 2025-11-23 Size : 710kb User : nedved
reaction-timer Downloaded：0: reaction timer by verilog
Date : 2025-11-23 Size : 976kb User : nedved
3bit-Wide-5to1-Mux Downloaded：0: 3bit Wide 5to1 Mux by verilog
Date : 2025-11-23 Size : 560kb User : nedved
calculator--EDA Downloaded：0: EDA design of programmable logic to design a simple decimal calculator can be used within the tube as the calculator keys and digital inputs and outputs, to complete within ten integer add, subtract, multiply, divide (qu
Date : 2025-11-23 Size : 128kb User : zhouminyan
character-rotation-on-multiple-7segment-displays. Downloaded：0: character rotation on multiple 7segment displays by verilog
Date : 2025-11-23 Size : 665kb User : nedved
JK_chufaqi Downloaded：0: JK flip-flop
Date : 2025-11-23 Size : 107kb User : 张同宇
6soft_247MHz_channel Downloaded：0: upstream channel deinterleaving lte demultiplexing: RTL: ack_addr_gen.vhd ack address generation data_addr_gen.vhd data address generation control unit de_interl_mux_con_top.vhd de_interl_mux_con_ctrl.vhd top de_interl_m
Date : 2025-11-23 Size : 196kb User : renliang

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