VHDL-FPGA-Verilog List Page 2328

VHDL-FPGA-Verilog list

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async_receiver Downloaded：0: verilog language, RS232 asynchronous receive and transmit modules
Date : 2025-11-23 Size : 1kb User : 何沐
DS18b20 Downloaded：0: This design uses no ROM 8051 as the main control chip. The interface circuit 8051 8155,2732 and ADC0809 and other chips. 8155 for the keyboard/LED display interface 2732 can be used as an external ROM memory 8031, ADC080
Date : 2025-11-23 Size : 104kb User : 高红
async_transmitter Downloaded：0: verilog language, RS232 asynchronous transmit module
Date : 2025-11-23 Size : 1kb User : 何沐
8b10b_dec Downloaded：0: vhdl language, 8b10b Decoder Module
Date : 2025-11-23 Size : 2kb User : 何沐
8b10b_enc Downloaded：0: vhdl language, 8b10b Decoder Module
Date : 2025-11-23 Size : 3kb User : 何沐
rs232 Downloaded：0: verilog language, RS232 Communication Program Design
Date : 2025-11-23 Size : 8kb User : 何沐
Program Downloaded：0: The VHDL code can be burned into the pedometer count completed GPGA function
Date : 2025-11-23 Size : 439kb User : 青争
33162769crcm Downloaded：1: FPGA-based error control coding, CRC cyclic check code VHDL code, including simulation file
Date : 2025-11-23 Size : 1kb User : Angela Lee
digital-frequency-meter Downloaded：0: The design of digital frequency meter, 1. Frequency Range: 1Hz-9999Hz. 2. Digital Display digits: 4-digit display. 3. The measured signal amplitude Ui = 0.5-5V (sine wave, triangle wave, square wave). 4. Measurement time
Date : 2025-11-23 Size : 50kb User : 翟明
LCD1602 Downloaded：0: LCD1602 controller
Date : 2025-11-23 Size : 2kb User : 车雪蓉
VHDL Downloaded：0: VHDL courseware, Lecture notes. English. introduction, language, hardware design.
Date : 2025-11-23 Size : 481kb User : 车雪蓉
Quartus Downloaded：1: Quartus the hardware design phase detector phase Quartus' s Quartus hardware circuit design of hardware circuit design phase
Date : 2025-11-23 Size : 4.36mb User : gudaoping

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