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VHDL-FPGA-Verilog list
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mplementation of a synchronous first in first out (FIFO) queue design with 16*8 RAM. A write FIFO that controls the data stream by writing enable terminals and controls read of data in the FIFO by the read enable. The op
Date : 2025-05-24 Size : 258kb User : 渔火

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altera lvds 2016-8-15
Date : 2025-05-24 Size : 1.47mb User : 下载一年

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There are three classic books of SystemVerilog, helpful for learning
Date : 2025-05-24 Size : 13.94mb User : trixie

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UVM entry example, a complete example of running through. These include the DUT code, the Testbench code,
Date : 2025-05-24 Size : 2.9mb User : 西麦

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Describes the use of spatran6 series of FPGA, serial asynchronous communication uart serial port to achieve the code
Date : 2025-05-24 Size : 352kb User : cy白菜

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Describes the use of spartan6 series FPGA, PLL PLL to achieve the functional code
Date : 2025-05-24 Size : 227kb User : cy白菜

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Using SPARTAN6 series of FPGA, to achieve the development of a basic snake game can be on the screen game, using verilog code
Date : 2025-05-24 Size : 6.99mb User : cy白菜

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Buy the beckoff company's ip kernel, provides a detailed datasheet and protocol description, attached to the ip kernel file, using verilog prepared, the platform can be set in the ISE itself
Date : 2025-05-24 Size : 4.47mb User : cy白菜

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simple state machine
Date : 2025-05-24 Size : 161kb User : tyne

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adder with overflow hint
Date : 2025-05-24 Size : 234kb User : tyne

Verilog Digital System Design
Date : 2025-05-24 Size : 21.75mb User : gss0001

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using FPGA verilog language a short code for frequtents
Date : 2025-05-24 Size : 3.12mb User : 点717
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