VHDL-FPGA-Verilog List Page 224

VHDL-FPGA-Verilog list

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axi_lite_user Downloaded：0: Axi_lite_user official sample, streamline function, apply to zynq series Axi bus
Date : 2025-05-23 Size : 4.42mb User : haixng
RGBtoYUV Downloaded：0: Transform RGB data of a bmp to YUV.
Date : 2025-05-23 Size : 36kb User : wonderful
VHDL实用教程_潘松_王国栋 Downloaded：0: This is a good tutorial for learning VHDL language. Very suitable for beginners to learn
Date : 2025-05-23 Size : 2.79mb User : 从小就够炫
串口通信 Downloaded：0: The program mainly to achieve FPGA serial communication, including source code and serial debugging tools
Date : 2025-05-23 Size : 768kb User : youngck
SPI_master Downloaded：0: simple program for SPI-Master
Date : 2025-05-23 Size : 1kb User : jxls378816
FPGA TFT 驱动 Downloaded：0: FPGA code for driving TFT.
Date : 2025-05-23 Size : 530kb User : 虞yuyuyuyuyu
spi Downloaded：0: SPI principle and its implemetation in verilog HDL
Date : 2025-05-23 Size : 24kb User : gentlegirl5
AD9512_coe Downloaded：0: AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clock performance data converter.
Date : 2025-05-23 Size : 1kb User : 小黄a小黄蛋
AD9512_ISE Downloaded：0: AD9512 provide multiplexed output clock distribution function, the input signal of up to 1.6 GHz.It has a low jitter and low phase noise characteristics, can greatly promote the clock performance data converter.
Date : 2025-05-23 Size : 4.83mb User : 小黄a小黄蛋
lab2 Downloaded：0: Verilog lab2 is used for learning vivado
Date : 2025-05-23 Size : 8kb User : Chappa
lab4 Downloaded：0: Verilog lab4 is used for learning vivado
Date : 2025-05-23 Size : 37kb User : Chappa
lab5 Downloaded：0: Verilog lab5 is used for learning vivado
Date : 2025-05-23 Size : 7kb User : Chappa

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