VHDL-FPGA-Verilog List Page 2200

VHDL-FPGA-Verilog list

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cdma Downloaded：0: In QII system using verilog developed a simple four-user CDMA system.
Date : 2025-11-24 Size : 4.06mb User : 洪依
count Downloaded：0: Very simple counter, under the invocation counter in the ISE IP cores, development has been the use verilog.
Date : 2025-11-24 Size : 340kb User : 洪依
uart Downloaded：0: HDL implementation of read and write operations on the 232, QuartusII project file
Date : 2025-11-24 Size : 465kb User : tianrong
DDS Downloaded：0: Developed under the MAXPLUSII verilog-based direct digital frequency synthesizer
Date : 2025-11-24 Size : 1.84mb User : 洪依
tongbu Downloaded：0: Clock synchronization algorithm using VERILOG developed to extract the clock from the data signal information,
Date : 2025-11-24 Size : 3.89mb User : 洪依
lcd_control2 Downloaded：0: Using verilog development 128_64 LCD driver,
Date : 2025-11-24 Size : 458kb User : 洪依
EDA-design-traffic-light Downloaded：0: In quartus2, based on the use of VHDL language simple traffic lights, traffic lights crossroads described, divided into primary and secondary channel, the second channel had no car, the green light has been the main road
Date : 2025-11-24 Size : 1kb User : 易为
SSD1963-LCD-controllers-driver Downloaded：1: SSD1963 LCD controllers driver Module for Microchip Graphics Library
Date : 2025-11-24 Size : 20kb User :
verilog-HDL-learning Downloaded：0: From scratch learn verilog HDL, including Altera experimental board schematic, xilinx test board schematics and source code of some experiments
Date : 2025-11-24 Size : 3.59mb User : susu
ReadFsm Downloaded：0: VHDL applet, read FSM. A job can be used as a VHDL。VHDL code and testbench.
Date : 2025-11-24 Size : 2kb User : 雪睿
FPGA_CPLD Downloaded：0: Sharing the experience of designing digital circuit with FPGA/CPLD
Date : 2025-11-24 Size : 912kb User : 李贺军
FPGA Downloaded：0: How to develop FPGA.
Date : 2025-11-24 Size : 21.11mb User : 李贺军

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