VHDL-FPGA-Verilog List Page 2195

VHDL-FPGA-Verilog list

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frenqucy Downloaded：0: Kang core using FPGA chip design company frequency meter, realize the frequency measurements.
Date : 2025-11-24 Size : 516kb User : stt
demo7-uart Downloaded：0: A compiled FPGA+ UART source for learning to modify
Date : 2025-11-24 Size : 465kb User : lishaoyi
dianyabiao Downloaded：0: Digital voltmeter, using the ADC0808, to test three-way voltage
Date : 2025-11-24 Size : 2kb User : 李寒
Diver_clk Downloaded：0: clock divider
Date : 2025-11-24 Size : 1kb User : shenzichao
FPGA Downloaded：0: FPGA-based SDRAM controller design method, using the method of the controller can easily control the SDRAM.
Date : 2025-11-24 Size : 11.43mb User : 呵呵
triangle_LFM Downloaded：0: DDS chip generated triangular wave linear FM signal of the FPGA program
Date : 2025-11-24 Size : 101kb User : TB-TB-MAN
processor_bkup Downloaded：0: It is the simple processor design.It will help to visualize how to develop different modules and then finally integrate them in top module.It also contains simulation files.
Date : 2025-11-24 Size : 133kb User : GajenJung
1602-simple Downloaded：0: Achieve fpga control lcd display driver, thinking clear and easy to understand, to help beginners learn!
Date : 2025-11-24 Size : 756kb User : 王帅
mux Downloaded：0: It is a simple mux created using vhdl.It will be helpful for beginners in vhdl.It also contains simulation file.
Date : 2025-11-24 Size : 47kb User : GajenJung
decoder Downloaded：0: It is a simple decoder created using vhdl in xilinx ise.It will helpful for beginners to create deocder using this.testbench for simulation is also created.
Date : 2025-11-24 Size : 415kb User : GajenJung
alarm_machine Downloaded：0: basic verilog HDL samples realizing an alarm clock circuit
Date : 2025-11-24 Size : 121kb User : YUHAN YAO
TIMER_tb_v1 Downloaded：0: testbench for the alarm clock circuit
Date : 2025-11-24 Size : 1kb User : YUHAN YAO

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