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VHDL-FPGA-Verilog list
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CY7C68013_DEMO
Downloaded:0
Cy7c68013 principle chart and procedures To realize the fpga and 68013 communication program code
Date
: 2025-11-24
Size
: 1.94mb
User
:
zhangxin
bujindianji
Downloaded:0
Just write the verilog stepper motor control program, 4-phase stepper motor is a 8 shot, three button control, respectively, forward, reverse, reset button. QQ942954258
Date
: 2025-11-24
Size
: 296kb
User
:
谷向前
seven_seg_ctrl
Downloaded:0
Seven Segment Control
Date
: 2025-11-24
Size
: 1kb
User
:
Biruk
fp_del
Downloaded:0
Pulse delete method to achieve any fractional frequency, duty drawback is not adjustable
Date
: 2025-11-24
Size
: 1kb
User
:
wen ping
fp_3
Downloaded:0
The same is to achieve any fractional frequency of the Verilog program, but to use a modular approach, variable duty cycle.
Date
: 2025-11-24
Size
: 1kb
User
:
wen ping
fp_top
Downloaded:0
In any fractional program joined the UART receiver module can receive the frequency factor and achieve frequency.
Date
: 2025-11-24
Size
: 5kb
User
:
wen ping
my_uart
Downloaded:0
A simple UART serial program, can send and receive data, but there is no parity and other validation data is correct.
Date
: 2025-11-24
Size
: 5kb
User
:
wen ping
AD1407
Downloaded:0
Introduced on the AD1407 VGA display features, including four VHDL files, and a pin file
Date
: 2025-11-24
Size
: 5kb
User
:
chenshi
shuzizhong
Downloaded:0
shuzizhong ,yejing ,1602
Date
: 2025-11-24
Size
: 1kb
User
:
张红星
FPGA-1602
Downloaded:0
Verilog 1602 on the preparation, for reference, study and learn, very helpful.
Date
: 2025-11-24
Size
: 617kb
User
:
王子
DAC_SINE_1K
Downloaded:0
Da with verilog write control output signal, the output frequency of 1khz
Date
: 2025-11-24
Size
: 1.77mb
User
:
林爻
VGA_CTL
Downloaded:0
Through a VGA display Chinese characters, written with verilog, are advanced experimental
Date
: 2025-11-24
Size
: 1.41mb
User
:
林爻
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.42
.43
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