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VHDL-FPGA-Verilog list
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EDA, verilog language written in frequency counter, one frequency measurement, one is a certain frequency as the signal source can be verified on the cycloneII, thank you! !
Date : 2025-11-24 Size : 637kb User : 谷向前

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And other precision frequency meter, verilog language, and can be verified on the development board, has tried
Date : 2025-11-24 Size : 1.2mb User : 谷向前

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AT89S51 2.4G production of high-precision digital frequency meter (by Anonymous), written in assembly language. Which contain schematic.
Date : 2025-11-24 Size : 420kb User : xiangiscoming

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This TI' s SPWM wave generation process, based on the MSP430 microcontroller, the chip used in the feedback control the duty cycle of the ADC
Date : 2025-11-24 Size : 39kb User : 周森未

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the use of DDS technology to make a sinusoidal signal generator
Date : 2025-11-24 Size : 233kb User : 周三强

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The source is the divider of the VHDL, have been carried out under the QUARTUS2 simulation and verification,
Date : 2025-11-24 Size : 295kb User : 周三强

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Four parallel multiplier VHDL source code has been validated, you can use
Date : 2025-11-24 Size : 5kb User : 周三强

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This is a simple VHDL example, but for beginners it is important to have validated hardware and software emulation
Date : 2025-11-24 Size : 248kb User : 周三强

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This a digital alarm clock design example, did not verify the success of yesterday, I hope some of the achievements in the field of VHDL colleagues for help
Date : 2025-11-24 Size : 86kb User : 周三强

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I have done before this is a basic example, model 60 counters, have a certain significance for beginners
Date : 2025-11-24 Size : 154kb User : 周三强

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8.9 ASK modulation and demodulation process, and VHDL simulation, I have verified
Date : 2025-11-24 Size : 1kb User : 周三强

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The source for infrared receiver, from the port to the received infrared data. Using QuartusII achieve, can be connected directly NiosII.
Date : 2025-11-24 Size : 730kb User : hlcheng
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