VHDL-FPGA-Verilog List Page 2003

VHDL-FPGA-Verilog list

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Spartan-3EPDemo--RS232P Downloaded：0: failed to translate
Date : 2025-09-19 Size : 3.87mb User : yu
48taps_fir Downloaded：0: Shaping filter can be modulated by the modulation wave band-pass filtering is accomplished, it can before the modulation baseband low-pass filter manner, both results are the same. In the modern all-digital modem, the sh
Date : 2025-09-19 Size : 90kb User : 尤恺元
verilog-hdl-example Downloaded：0: verilog hdl tutorial 135 cases
Date : 2025-09-19 Size : 166kb User : INTER
con1 Downloaded：0: 4 bit convoltion with vhdl.
Date : 2025-09-19 Size : 1kb User : Rakesh tirupathi
Xilinx-Training-2010 Downloaded：0: Xilinx 2010, training of technical documentation, development of the FPGA is very helpful
Date : 2025-09-19 Size : 41.56mb User : 何立志
Traffic Downloaded：0: Traffic Light Controller For 4 main road
Date : 2025-09-19 Size : 1kb User : rizki
8051 Downloaded：0: verilog 8051 source code ic
Date : 2025-09-19 Size : 2kb User : 曾平
carry_lookahead_add4 Downloaded：0: 4-bit look-ahead adder, gate-level circuit
Date : 2025-09-19 Size : 282kb User : 陈振睿
BCDadd8 Downloaded：0: 8-bit BCD adder, BCD said that 4bit represents a decimal number, range is 0000-0110, verilog code
Date : 2025-09-19 Size : 249kb User : 陈振睿
password Downloaded：0: verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to
Date : 2025-09-19 Size : 565kb User : 陈振睿
MSequenceGenerator Downloaded：0: 5 of the M-sequence generator, verilog code. 5 using a primitive polynomial f (x) = x ^ 5+ x ^ 2+1
Date : 2025-09-19 Size : 107kb User : 陈振睿
Hamming_Encoder Downloaded：0: (7,4) Hammming Encoder, verilog code. Generator matrix is G = [1,0,0,0 0,1,0,0 0,0,1,0 0,0,0,1 1,1,1,0 0,1, 1,1 1,1,0,1]
Date : 2025-09-19 Size : 80kb User : 陈振睿

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