VHDL-FPGA-Verilog List Page 1945

VHDL-FPGA-Verilog list

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Dchufa Downloaded：0: Using hardware description language design of the D flip-flop, the modern logic
Date : 2025-09-19 Size : 2kb User : 罗风
fenpin Downloaded：0: Using hardware description language design divider, modern logic
Date : 2025-09-19 Size : 3kb User : 罗风
jiafaqi Downloaded：0: Hardware description language design adder, modern logic devices
Date : 2025-09-19 Size : 2kb User : 罗风
xujuxuanzhe Downloaded：0: Also designed using hardware description language data selector, modern logic devices
Date : 2025-09-19 Size : 2kb User : 罗风
port-must-be-called-a-key-law-sweep Downloaded：0: A new key scanning method, with five IO ports can scan 20 keys.
Date : 2025-09-19 Size : 150kb User : sdfsdf
digital_clock Downloaded：0: verilog digital clock/4 bits/ up_down/stopwatch
Date : 2025-09-19 Size : 803kb User : shisaiyu
display_combine Downloaded：0: This is the Verilog HDL students to do the job. Is a digital clock. A clock, stopwatch and other functions. The original.
Date : 2025-09-19 Size : 826kb User : shisaiyu
Verilog Downloaded：0: verilog digital clock
Date : 2025-09-19 Size : 12kb User : mini
uart1 Downloaded：0: vhdl uart module. this file is used to transfer programs frm fpga xilinx spartam 3e kit to desktop pc through rs232 serial port.
Date : 2025-09-19 Size : 276kb User : pingakshya
S9_PS2_LCD Downloaded：0: ps2+12864, verilog source code. .
Date : 2025-09-19 Size : 759kb User : 王半田
S10_PS2_RS232 Downloaded：0: verilog+ ps2+ rs232
Date : 2025-09-19 Size : 1.54mb User : 王半田
S13_VIDEO_IN_S_VIDEO Downloaded：0: verilog+ ps2+ rs232
Date : 2025-09-19 Size : 2.22mb User : 王半田

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