This is the Verilog HDL students to do the job. Is a digital clock. A clock, stopwatch and other functions. The original.

display_combine
...............\db
...............\..\display_combine.asm.qmsg
...............\..\display_combine.asm_labs.ddb
...............\..\display_combine.cbx.xml
...............\..\display_combine.cmp.bpm
...............\..\display_combine.cmp.cdb
...............\..\display_combine.cmp.ecobp
...............\..\display_combine.cmp.hdb
...............\..\display_combine.cmp.logdb
...............\..\display_combine.cmp.rdb
...............\..\display_combine.cmp.tdb
...............\..\display_combine.cmp0.ddb
...............\..\display_combine.cmp2.ddb
...............\..\display_combine.cmp_bb.cdb
...............\..\display_combine.cmp_bb.dfp
...............\..\display_combine.cmp_bb.hdb
...............\..\display_combine.cmp_bb.logdb
...............\..\display_combine.cmp_bb.rcf
...............\..\display_combine.dbp
...............\..\display_combine.db_info
...............\..\display_combine.eco.cdb
...............\..\display_combine.eds_overflow
...............\..\display_combine.fit.qmsg
...............\..\display_combine.hier_info
...............\..\display_combine.hif
...............\..\display_combine.map.bpm
...............\..\display_combine.map.cdb
...............\..\display_combine.map.ecobp
...............\..\display_combine.map.hdb
...............\..\display_combine.map.logdb
...............\..\display_combine.map.qmsg
...............\..\display_combine.map_bb.cdb
...............\..\display_combine.map_bb.hdb
...............\..\display_combine.map_bb.logdb
...............\..\display_combine.pre_map.cdb
...............\..\display_combine.pre_map.hdb
...............\..\display_combine.psp
...............\..\display_combine.pss
...............\..\display_combine.rtlv.hdb
...............\..\display_combine.rtlv_sg.cdb
...............\..\display_combine.rtlv_sg_swap.cdb
...............\..\display_combine.sgdiff.cdb
...............\..\display_combine.sgdiff.hdb
...............\..\display_combine.signalprobe.cdb
...............\..\display_combine.sim.cvwf
...............\..\display_combine.sim.hdb
...............\..\display_combine.sim.qmsg
...............\..\display_combine.sim.rdb
...............\..\display_combine.sld_design_entry.sci
...............\..\display_combine.sld_design_entry_dsc.sci
...............\..\display_combine.syn_hier_info
...............\..\display_combine.tan.qmsg
...............\..\prev_cmp_display_combine.asm.qmsg
...............\..\prev_cmp_display_combine.fit.qmsg
...............\..\prev_cmp_display_combine.map.qmsg
...............\..\prev_cmp_display_combine.qmsg
...............\..\prev_cmp_display_combine.sim.qmsg
...............\..\prev_cmp_display_combine.tan.qmsg
...............\..\wed.wsf
...............\display.bsf
...............\display.v
...............\display.v.bak
...............\display_4outputs.bdf
...............\display_combine.asm.rpt
...............\display_combine.cdf
...............\display_combine.done
...............\display_combine.dpf
...............\display_combine.fit.rpt
...............\display_combine.fit.smsg
...............\display_combine.fit.summary
...............\display_combine.flow.rpt
...............\display_combine.map.rpt
...............\display_combine.map.smsg
...............\display_combine.map.summary
...............\display_combine.pin
...............\display_combine.pof
...............\display_combine.qpf
...............\display_combine.qsf
...............\display_combine.qws
...............\display_combine.sim.rpt
...............\display_combine.sof
...............\display_combine.tan.rpt
...............\display_combine.tan.summary
...............\display_combine.v
...............\display_combine.v.bak
...............\display_combine.vwf
...............\display_combine1.bdf
...............\display_combine2.bdf
...............\display_combine3_stopcount.bdf
...............\display_combine_assignment_defaults.qdf
...............\display_withsel.v
...............\frequency_div.bdf
...............\frequency_divider.v
...............\frequency_divider.v.bak
...............\led1.v
...............\led1_1.bdf
...............\led2.v
............

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