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VHDL-FPGA-Verilog list
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Description language with verilog barrel shifter.
Date : 2025-09-18 Size : 958kb User :

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Verilog description language with the MIPS and ARM ALU program.
Date : 2025-09-18 Size : 2.41mb User :

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Verilog description language with the MIPS32-bit CPU.
Date : 2025-09-18 Size : 2.58mb User :

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antidad_a EQU s0 talto EQU s1 Rename register sX with tbajo EQU s2 indicador EQU s3 cantidad_b EQU S4 Define constant , assign value name ROM output file generated by pBlazIDE assembler VHDL "ROM_form.vhd",
Date : 2025-09-18 Size : 1.01mb User : Jorge

DC Motor Based on VHDL controller and its control, the overall structure of the control system, the next bit machine is the high-frequency fatigue test machine controller core. Control the testing machine used to impleme
Date : 2025-09-18 Size : 3kb User : moyeo

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FFT in VHDL source code
Date : 2025-09-18 Size : 29kb User : 周鑫

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clk jiaozhun shixian shujuzhunqueduru
Date : 2025-09-18 Size : 1kb User : 海怒

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FPGA-based 17-order FIR filter VHDL code. File with the FIR digital filter theory introduction.
Date : 2025-09-18 Size : 898kb User : 周鑫

General-purpose memory VHDL code base. fifo, ram register code and test modules.
Date : 2025-09-18 Size : 23kb User : 周鑫

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ORCAD PSpice versatile Chinese icon (simulation) tutorial
Date : 2025-09-18 Size : 7.41mb User : 土豆

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LCD1602 interfacing routines for FPGA (EP2C5-EP2C8)
Date : 2025-09-18 Size : 1kb User : acido cinico

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FPGA implementation and other precision measuring frequency, very accurate, I test
Date : 2025-09-18 Size : 872kb User : swann
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