VHDL-FPGA-Verilog List Page 1912

VHDL-FPGA-Verilog list

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stopwatch-programmer- Downloaded：0: stopwatch verilog
Date : 2025-09-18 Size : 3kb User : 董福
60s-StopWatch--verilog Downloaded：0: stopwatch verilog
Date : 2025-09-18 Size : 573kb User : 董福
generator.new Downloaded：0: AVR DDS Generator. It designed for AtMega16 or similar. It can generate Sinus, Saw, Square and triangle.
Date : 2025-09-18 Size : 227kb User : Martin Valensky
UART_IF Downloaded：0: The source code achieve universal serial interface receive and send. The serial interface of data transfer into bus data flow. Facilitate further on data processing.
Date : 2025-09-18 Size : 150kb User : 周鑫
luan-van Downloaded：0: design calculator using verilog
Date : 2025-09-18 Size : 10kb User : Nick
Verilog-HDL Downloaded：0: If you have not found a suitable learning HDL information, then look at the document it. Might help you to do we
Date : 2025-09-18 Size : 3mb User : 苏华强
FPGA-chuankoutongxin Downloaded：0: Fpga implementation of serial communication, use of top-down design methods for asynchronous serial ip nuclear
Date : 2025-09-18 Size : 23.06mb User : 李
1 Downloaded：0: High-frequency simulation of electronic technology, including: LC frequency selection. AM, FM, DSB, SSB modulation. EWB simulation using
Date : 2025-09-18 Size : 70kb User : 张
state_machine Downloaded：0: Stepper motor control state machine model supporting the development board: A-C8V4
Date : 2025-09-18 Size : 1kb User : 杨瑞
serial Downloaded：0: Supporting the development of serial communication boards and computer models: A-C8V4
Date : 2025-09-18 Size : 3kb User : 杨瑞
VGA_Module Downloaded：0: VGA LCD display Chinese characters supporting the development board Model: A-C8V4
Date : 2025-09-18 Size : 2kb User : 杨瑞
pwm Downloaded：0: PWM experiment VGA LCD display Chinese characters
Date : 2025-09-18 Size : 1kb User : 杨瑞

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